Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-04-28
2002-04-30
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06381707
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the use of partially defective memory chips or memory arrays. More particularly, the present invention relates to the use of a partially defective memory array to create a non-defective memory array.
BACKGROUND AND SUMMARY OF THE DISCLOSURE
As is well known in the art, during the production of monolithic memory devices from silicon wafers, memory storage cells can become defective and unreliable. These defective cells can be the result of a number of causes, such as impurities introduced in the process of manufacturing the monolithic memory device from the silicon wafer, or localized imperfections in the silicon substrate itself.
Often, while some memory cells in a particular memory array are defective, many other cells on the same memory array are not defective, and will work reliably and accurately. In addition, it is often the case that the defective cells are localized and confined to particular regions within the memory array. The remaining, non-defective regions, however, can be relied upon to provide a consistent and accurate representation of the information in the storage cell. What is needed, therefore, is a system or method for salvaging non-defective portions of memory arrays, even where the non-defective portions are not localized to any particular outputs on the memory module or memory array. Such a system preferably works transparently to the memory controller and is compatible with existing systems.
SUMMARY OF INVENTION
The present invention relates to techniques for salvaging non-defective portions of a memory array or memory module. In one embodiment of the invention, the invention relates to a computer comprising: (a) a processor; (b) a memory controller connected to the processor by a host bus, wherein the memory controller generates an address; (c) a memory module that is accessible to the memory controller through an address bus, wherein the memory module includes a defective portion and a non-defective portion; and (d) a decoder. The decoder comprises inputs that receive at least a portion of the address from the memory controller, logic that modifies the address so that the defective portion of the memory module is not accessed, and logic that places at least a portion of the modified address on the address bus.
In another embodiment of the present invention, the present invention relates to a memory controller that accesses a memory module over an address bus, wherein the memory module has a defective portion and a non-defective portion. The memory controller comprises: (a) inputs for receiving an address from a processor over a host bus; (b) address outputs connected to the address bus; (c) logic that modifies the address received from the processor so that the defective portion of the memory module is not accessed; and (d) logic that places the modified address at the address outputs.
Additional embodiments and features, and the nature of the present invention may be more clearly understood by reference to the following detailed description of the invention, the appended claims, and to the several drawings herein.
Additional embodiments and features, and the nature of the present invention may be more clearly understood by reference to the following detailed description of the invention, the appended claims, and to the several drawings herein.
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Mic
Larsen Corey
Weber Richard
Beausoleil Robert
Bonzo Bryce P.
Knobbe Martens Olson & Bear LLP
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