System for debugging throughput deficiency in an...

Details System for debugging throughput deficiency in an... System for debugging throughput deficiency in an...

2011-07-19

2011-07-19

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S060000, C710S260000, C717S124000

Reexamination Certificate

active

07984206

ABSTRACT:
A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value.

REFERENCES:
patent: 5542076 (1996-07-01), Benson et al.
patent: 5717932 (1998-02-01), Szczepanek et al.
patent: 5778194 (1998-07-01), McCombs
patent: 5875119 (1999-02-01), Bauman et al.
patent: 6105064 (2000-08-01), Davis et al.
patent: 6415243 (2002-07-01), Mann
patent: 6487631 (2002-11-01), Dickinson et al.
patent: 6493655 (2002-12-01), Fuse
patent: 6615370 (2003-09-01), Edwards et al.
patent: 6732311 (2004-05-01), Fischer et al.
patent: 6816989 (2004-11-01), Litt
patent: 7065598 (2006-06-01), Connor et al.
patent: 7107362 (2006-09-01), Wheless et al.
patent: 7107632 (2006-09-01), Huff et al.
patent: 7275191 (2007-09-01), Adkisson
patent: 7434108 (2008-10-01), Moyer et al.
patent: 2002/0026553 (2002-02-01), Saito
patent: 2004/0015744 (2004-01-01), Klotz et al.
patent: 2004/0019738 (2004-01-01), Kahn et al.
patent: 2006/0212263 (2006-09-01), Koehler et al.
patent: 2007/0028010 (2007-02-01), Krasnansky

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