System for data stream packer and unpacker integrated circuit wh

Details System for data stream packer and unpacker integrated circuit wh System for data stream packer and unpacker integrated circuit wh

1998-06-02

2000-05-16

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

710 4, 710 52, 710 71, G06F 1300

Patent

active

060650664

ABSTRACT:
A system is provided for packing and unpacking data being transferred between a serial network connection and a parallel system bus of a computer system. In the receive direction, this is achieved by unpacking fixed length serial data packets into a receive payload buffer. Data is then incrementally fetched from the receive payload buffer and stored in a first latch. The contents of the first latch are then transferred to a second latch, while additional fixed length serial data packets are store in the first latch. The data stored in the first and the second latch is then aligned in an aligner module depending on an address offset in a host computer memory and stored in an unpacker module. Variable length data is then retrieved from the unpacker module and stored in the host computer memory. In the send direction, this is achieved by aligning and packing variable length data transferred into a send payload buffer. Variable length data is first stored in a first latch. The contents of the first latch are then transferred to a second latch, while additional variable length is stored in the first latch. The data stored in the first and the second latch is then aligned in an aligner module depending on an address offset in a host computer memory and stored in a packer module. Fixed length data packets are then retrieved from the packer module and stored in a send payload buffer.

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IBM TBD Dishon et al, "Variable-length data assembler", vol. 19, No. 12, Oct. 1976, pp. 1892-1895.

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