System for data dependent voltage bias level

Details System for data dependent voltage bias level System for data dependent voltage bias level

2000-03-03

2002-01-29

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter compensation

Reexamination Certificate

active

06342848

ABSTRACT:

BACKGROUND
1. Field
The invention relates to providing direct-current (DC) isolation for electrical signals.
2. Background Information
As is well-known, a series capacitor, as illustrated in
FIG. 2
, may be employed to block direct current (DC) voltage levels on a DC balanced signal. In this context, the term “DC balanced” refers to the time average of the signal converging to a DC, fixed signal level that is independent of the data signal values, typically zero volts for differential signaling. This is illustrated in
FIG. 2
in which a capacitor
230
is coupled in series with an operational amplifier
210
. For the embodiment illustrated in
FIG. 2
, V
bias
provides the center point for the signal V
int
.
FIG. 3
illustrates the corresponding signals along a time axis. The biasing scheme operates satisfactorily so long as the signal has an average value independent of data signals. In a system employing binary digital signals, this means a balanced number of “ones” and “zeros.” However, in many systems, this balancing of ones and zeros is not assured. For example, although the invention is not limited in scope in this respect, the 1394A protocol specification, Draft 2.0, dated Mar. 15, 1998, available from the Institute of Electrical and Electronic Engineers (IEEE), (hereinafter, “1394A”), does not ensure a balanced number of ones and zeros. Therefore, a long run of zeros may cause the internal node, such as V
int
in
FIG. 2
, to drift up to the bias level instead of remaining at the level indicating a “zero.” This effect may be more pronounced in multi-level systems, where multiple voltage signal levels are sensed. For example, the 1394A specification employs three logic levels, zero, “z,” and one. Therefore, if a long string of zeros were sent, V
int
would drift up and result in a z being mistakenly interpreted, as illustrated in
FIG. 3
, for example. A need, therefore, exists to address this shortcoming in such unbalanced systems.
SUMMARY
Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling.
Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the comparator output signal.


REFERENCES:
patent: 5661482 (1997-08-01), Shou et al.
patent: 6075476 (2000-06-01), Johnson et al.
“Performance Consumer Desktop Platform,” Sep. '98 Intel Developer Forum, Sep. 1998, pp. 17-29.

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