System for creating a physical hierarchy of a chip without...

Details System for creating a physical hierarchy of a chip without... System for creating a physical hierarchy of a chip without...

2006-10-03

2006-10-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07117473

ABSTRACT:
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.

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Wang, Maogang, et al., “Multi-Million Gate FPGA Physical Design Challenges,” ICCAD '03, Nov. 11-13, 2003, pp. 891-898, Available from ICCAD, San Jose, California, USA.

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