Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-05-19
2001-02-06
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C714S040000, C341S094000
Reexamination Certificate
active
06185649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a peripheral connect interface (PCI) addressing scheme, and more particularly, to an auto detection and correction logic for a PCI bus addressing scheme.
2. Description of Related Art
A PCI bus interfaces a master to a number of slave peripheral devices through the PCI bus. Each of the peripheral devices has an associated base address register, typically 32 bits in length. The PCI convention specifies that if the peripheral device has a certain amount of memory that is addressable, the master loads an address signal, of is a particular format, into the base address register.
FIG. 1
is a table of specified base address signals according to the amount of memory available under PCI convention. For example, if all 4 gigabytes (32 bits) of memory are available, the base address register is loaded with all 32 bits each with a value of “0” or “0 . . . 0.” If there are two gigabytes of memory available, the first or left most bit is denoted “1” followed by all 31 bits of “0”s. Thus, if two gigabytes of memory are available, the base address register is loaded with “1 0 0 . . . 0.” If only one gigabyte of memory is available, then the two left most bits are denoted “1” and followed by all “0”s, thereby loading the base address register with “1 1 0 0 . . . 0.”
Sometimes the base address register may be loaded with an illegal address. One type of illegal address is an out of range address or an address of the wrong size. For example, an address 16 bits in length is an illegal address. Prior art to correct and illegal address have included U.S. Pat. Nos. 5,555,250; 5,649,162; 5,649,129; 5,337,264; and 5,287,321.
Another type of illegal address is an address of the correct size, but illegal in that the address violates PCI convention. For example, an address such as “1 1 0 1 0 0 . . . 0” is an illegal address because a “1” is to the right of a “0”. According to PCI convention, a “0” may not be the left adjacent bit of a “1”.
There are a number of methods for detecting an illegal address. For example, an out of range address may be detected with a detection scheme that uses combinatorial logic. However, currently there is no apparatus or method for detecting an illegal addresses, that violates the PCI convention, as described, above, and corrects it.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus that automatically corrects any illegal address that is to be loaded to a base address register. In accordance with the present invention, a current bit is read. If the current bit is “0,” the address is legal regardless of the value of the left adjacent bit. However, if the current bit is “1,” the addressing scheme reads the left adjacent bit to determine if the address is legal. If the left adjacent bit is “1,” the address is legal. However, if the left adjacent bit is “0,” the address is illegal and the current bit is corrected to “0.”
REFERENCES:
patent: 4658399 (1987-04-01), D'Angio et al.
patent: 4677627 (1987-06-01), Hong
patent: 5023612 (1991-06-01), Liu
patent: 5235603 (1993-08-01), McNesby et al.
patent: 5287321 (1994-02-01), Shiffer, II
patent: 5377264 (1994-12-01), Lee et al.
patent: 5510786 (1996-04-01), Gorshe
patent: 5555250 (1996-09-01), Walker et al.
patent: 5611065 (1997-03-01), Alferness et al.
patent: 5649129 (1997-07-01), Kowert
patent: 5649162 (1997-07-01), Klein et al.
Elamin Abdelmoniem
Lee Thomas C.
Smith Andrew V.
Toshiba America Electronic Components Inc.
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