Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-08-05
1999-05-18
Lee, Thomas C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395842, 395872, 711158, G06F13/20;13/28
Patent
active
059059052
ABSTRACT:
A host computer having a CPU and a FIFO memory connected to an I/O adapter for the exchange of I/O information between the host and the adapter. The host writes I/O commands and stores them in a relatively small FIFO memory of the host. The I/O commands are then copied to a relatively large I/O memory array in the I/O adapter where they are stored until the I/O command is completed. The FIFO is then free for use by other I/O commands from the host CPU. I/O completion information is returned to a completion queue in the host by the adapter. This information includes completion status and an indication of the number of I/O commands copied to the adapter from the host FIFO. This allows the CPU to invalidate and reuse all FIFO locations containing I/O commands that have been copied from the FIFO to the adapter I/O array.
REFERENCES:
patent: 4875155 (1989-10-01), Iskiyan et al.
patent: 4901232 (1990-02-01), Harrington et al.
patent: 5737520 (1998-04-01), Gronlund et al.
patent: 5752078 (1998-05-01), Delp et al.
patent: 5802343 (1998-09-01), Fandrich et al.
Dailey Aaron J.
Gibson Kenneth J.
Kroun Jack P.
Quicksall Edward S.
Adaptec, Inc.
Lee Thomas C.
Perveen Rehana
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