Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1998-10-12
2001-04-03
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S495000
Reexamination Certificate
active
06212627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems, and specifically, to data manipulation instructions for enhancing value and efficiency of parallel instructions.
2. Background Information
To improve the efficiency of multimedia applications, as well as other applications with similar characteristics, a Single Instruction, Multiple Data (SIMD) architecture has been implemented in computer systems to enable one instruction to operate on several operands simultaneously, rather than on a single operand. In particular, SIMD architectures take advantage of packing many data elements within one register or memory location. With parallel hardware execution, multiple operations can be performed on separate data elements with one instruction, resulting in a significant performance improvement.
In many graphics applications, specifically three-dimensional (“
3
D”) graphics applications, there are manipulation of scenes that have objects such as triangles and polygons, which are rotated, scaled, etc. The range of numbers in, for example, a thirty-two-bit register is from 0 to 2
32
−1. However, in many instances, the values of the objects may need to be represented by a floating-point number because a bigger number range is required or the number is not a whole number (e.g., due to introduction of angles). Therefore, these values must be converted to floating-point numbers and moved to the floating-point registers. Currently, to go from a SIMD packed integer data item to a SIMD packed floating-point data item, on the floating-point side (i.e., floating-point registers) of a processor, requires numerous instructions.
FIG. 1
illustrates a conventional technique of converting a SIMD packed integer data item to a SIMD packed floating-point data item. Referring to
FIG. 1
, a SIMD packed data item having integer data elements I
1
and I
2
are contained in a first floating-point register (“FR
1
”). The packed data item is transferred from FR
1
to a first integer register (“IR
1
”) on the integer side of the processor, in response to a first instruction (INST
1
). This is done because of the more robust instructions available on the integer side of the processor. Once on the integer side of the processor, the first data element I
1
is placed in the lower order bits of a second integer register (“IR
2
”) and the sign of I
1
is extended in the higher order bits of IR
2
, in response to a second instruction (INST
2
). In response to a third instruction (INST
3
), IR
1
is arithmetically shifted right from the higher order bits to the lower order bits, and the sign of I
2
is shifted in the higher order bits.
In response to fourth and fifth instructions (INST
4
and INST
5
), the data items contained in IR
2
and IR
1
are transferred to floating-point registers FR
1
and FR
2
, respectively. The data items in FR
1
and FR
2
are now on the floating-point side of the processor. In response to sixth and seventh instructions (INST
6
and INST
7
), the integer data items in FR
1
and FR
2
are converted to corresponding floating-point data items F
1
and F
2
, in extended precision format (82 bits). The data items F
1
and F
2
are each represented by a mantissa (M
1
and M
2
) and an exponent (E
1
and E
2
). Responsive to eight and ninth instructions (INST
8
and INST
9
), the data items F
1
and F
2
are stored in memory at locations A and A+1, respectively. The data items F
1
and F
2
are stored as single precision values (32 bits). In response to a tenth instruction (INST
10
), the data items stored in memory locations A and A+1 are loaded in FR
1
(64 bits), providing a floating-point data item. As can be seen, the conversion of a SIMD packed integer to a SIMD packed float requires ten instructions, three of which are memory instructions. Memory instructions are very costly as compared to non-memory instructions. This conversion from SIMD packed integer to SIMD packed float may be required for thousands of data items in an application.
Accordingly, there is a need in the technology for a method and apparatus for reducing the number of instructions required to covert a SIMD packed integer to a SIMD packed float.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. A method includes moving the first data element of the integer data item to a first element of a first intermediate data item and extending a sign of the first data element into all bit positions of a second data element of the first intermediate data item. The second data element of the integer data item is moved to a first data element of a second intermediate data item and a sign of the second data element is extended into all bit positions of a second data element of the second intermediate data item. The method then converts the first and second intermediate data items from integer data items to respective floating-point data items, and packs the first and second intermediate floating-point data items to first and second data elements of a result.
REFERENCES:
patent: 5892960 (1999-04-01), Seide
patent: 5995122 (1999-11-01), Hsieh et al.
Goldman, Gary et al., UltraSPARC-II(tm): The Advancement of UltraComputing, IEEE, 1996.*
Lee, Ruby et al., 64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture, IEEE, 1996.*
Shipnes, Julie, Graphics Processing with the 88110 RISC Microprocessor, IEEE 1992.*
Arakawa, Fumio, SH4 RISC Multimedia Microprocessor, IEEE Micro, 1998.
Dulong Carole
Golliver Roger A.
Blakely , Sokoloff, Taylor & Zafman LLP
Ellis Richard L.
Intel Corporation
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