Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-09-16
2001-05-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06226776
ABSTRACT:
CROSS-REFERENCE TO MICROFICHE APPENDIX
Appendix A, which is a part of the present disclosure, is a microfiche appendix consisting of two sheets of microfiche having a total of 176 frames. Microfiche Appendix A is a source code listing of a portion of the code comprising one embodiment of a system for converting hardware designs in a highlevel programming language (ANSI C) into a register transfer level hardware description language (Verilog), which is described in more detail below.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as they appear in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
This invention relates to configuring digital circuits, especially computationally intensive digital circuitry, such as field programmable gate arrays (FPGAs) and other programmable logic hardware and application specific integrated circuits (ASICs), and, more particularly, to computer aided design of such computationally intensive digital circuitry. Specifically, one embodiment of the invention provides a system for converting a hardware design rendered in a high-level programming language, such as ANSI C, into an actual hardware implementation, for example, as an FPGA.
Various persons have previously attempted to address the long-felt need for an easy approach.to designing computationally intensive digital circuits, such as FPGAs. The prior art evidences two divergent approaches for designing actual implementations for digital hardware.
One prior art approach has been to create a specific hardware description language (HDL) for designing hardware. Various commercially available HDLs have been developed, such as Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, and PALASM. After a hardware design is rendered in an HDL, the HDL design is processed into a gate-level hardware representation using one of various hardware- or manufacturer-specific synthesis programs to interpret the HDL design. Then, the gate-level representation is reduced to an actual hardware implementation using conventional physical design tools.
HDLs are specific computer aided design tools for hardware designers and require a level of expertise in the use of the particular HDL being employed to render a hardware design and are difficult to learn and use. See, for example, Tuck, B., “Raise Your Sights to the System Level,” Computer Design, June, 1997, pp. 53, 69. Therefore, only persons who frequently design hardware typically use HDLs. If a circuit application arises in which design and implementation of an FPGA is economically justified, the vast majority of persons must retain an expert or confront the difficult task of learning an HDL. Furthermore, these HDLs are not typically universal for the design of FPGAs, since many HDLs are supported by only a single or a limited number of hardware manufacturers. Consequently, even experienced users of an HDL, such as fill-time hardware designers, may not be sufficiently familiar with other HDLs to be able to render a design which can be implemented in a variety of hardware systems from a number of different hardware manufacturers. There is therefore a need for an easy-to-use, universal computer aided hardware design tool by both experts and occasional hardware designers as well.
A second prior art approach recognizes that the development of computationally intensive hardware would be available to a wider population of persons if hardware designs could be rendered in a standard high-level programming language which is more universally known, easier to use, and more frequently employed than HDLs. One such high-level programming language is ANSI C. Others, many of which have several extensions, are: APL, Ada, Algol, B, Basic, Kernighan & Ritchie C, C++, CLOS, COBOL, Clu, Common Lisp, Coral, Dylan, Eiffel, Emacs Lisp, Forth, Fortran, IDL, Icon, Java, Jovial, Lisp, LOGO, ML, Modula, Oberon, Objective C, PL/I, PL/M, Pascal, Postscript, Prolog, Python, RTL, Rexx, SETL, Simula, Sather, Scheme, Smalltalk, Standard ML, TCL, and TRAC.
Unfortunately, prior art attempts to base computer aided hardware design tools on high-level programming languages have been incomplete. Consequently, these attempts to realize the goal of providing an effective tool for designing hardware using a high-level programming language have not achieved widespread use. All the prior art attempts have each suffered three or more of the following shortcomings:
1. Prior art computer aided hardware design tools generate so many unhandled exceptions and language restrictions when presented with typical high-level language programs (e.g., a C program) that it renders such tools virtually useless for practical hardware design. Therefore, persons using such tools are required to read manuals and attempt to create work-arounds for portions of the high-level programming language, which are not implemented.
2. Hardware generated using prior art computer aided hardware design tools is typically based on simple line-by-line, table-driven translation and as such does not contain the necessary widely scoped optimizations that produce practical and useful hardware designs for most applications.
3. Design output of the prior art computer aided hardware design tool can be in so-called “behavioral HDL” for modeling hardware but in many cases cannot be synthesized by existing synthesis programs into a gate-level representation of the hardware.
4. Prior art computer aided hardware design tools attempt to generate designs which only apply to a single manufacturer hardware family, such as the creation of an XNF file for the Xilinx XC4000 FPGA family.
5. The language employed by prior art computer aided hardware design tools has added and limited so many constructs that it is difficult to consider the employed language as the high-level programming language purportedly being emulated. That is, the result language is more like a new specialized HDL.
Considered in more detail, one prior art computer aided hardware design tool which purports to enable persons to render hardware designs in a high-level programming language is Transmogrifier (TMCC), a tool developed in 1994-1995 at the University of Toronto, Canada. A comprehensive compiler typically requires at least ten times the 4,900 lines of code which comprise TMCC. TMCC does not support such common C-type programming language features as “do” loops, “for” loops, local or global arrays (i.e., the [ ] operator), the operators ->, unary &, unary *, etc.
Another prior art computer aided hardware design tool is NLC developed at Ecole Polytechnique Federale de Lausanne, Switzerland in 1994-1995. The code for NLC is based on the public domain compiler known as GNU. Like Transmogrifier, NLC supports a severely restricted subset of C-type programming language, for example, “for” loop bounds must be known at compile time, and functions cannot return values. The NLC library generates hardware designs only in XNF format for the Xilinx XC4000 FPGA family.
A prior art computer aided design tool for hardware which purports to be a high-level programming language is Handel-C, originally developed at the Computing Laboratory of Oxford University, England in 1995-1996 and presently supported by Embedded Solutions Limited in Berkshire, England. Although Handel-C has been described by its developers as a subset of ANSI C with some Occam-like extensions, the vast majority of ANSI C programs cannot be processed by Handel-C. For example, functions in Handel-C must be declared in main, have no return values, and have no parameters. There are no structs, unions, enums, struct bit fields, character constants, externs, pointers, etc. The output of Handel-C is in XNF format for the Xillinx XC4000 FPGA family. Since the language is so unlike a high-level programming language, Handel-C is better classified as an HDL for
Coleman Denis R.
Panchul Yuri V.
Soderman Donald A.
Garbowski Leigh Marie
Milks, III William C.
Russo & Hale LLP
Smith Matthew
Synetry Corporation
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