Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2001-02-08
2004-02-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S310000, C713S322000
Reexamination Certificate
active
06694443
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuits, and more particularly to a microprocessor having hardware controlled power management.
BACKGROUND OF THE INVENTION
Increasingly, electronic circuit manufacturers need to reduce the power consumption of their boards. The conservation of power is particularly important in portable electronic devices, such as laptop or notebook computers, where the product is specifically designed for use in situations where power outlets are not available. Since laptop and notebook computers must operate using internal batteries or rechargeable battery packs for extended periods of time, the conservation of battery power becomes a primary concern.
In a laptop or notebook computer, the largest consumer of power is the display. The proportion of power consumed by the display will vary depending on the technology used. Thus, laptop and notebook computer manufacturers have disabled the power to the display during periods of inactivity. Decoupling the display from the power supply can be accomplished with fairly simple circuitry.
The next largest consumer of power on a laptop or notebook computer is the CPU motherboard microprocessor. Heretofore, computer manufacturers have used one or two techniques for reducing power consumption of the microprocessor during periods of inactivity. One technique reduces the speed of the system clock to a fraction of the normal operating frequency during periods of inactivity. Since the power consumption of the microprocessor is proportional to the frequency, reducing the frequency of the system clock also reduces the power consumption of the microprocessor. In an Intel 80386DX microprocessor (manufactured by Intel Corporation of Santa Clara, Calif.), reducing the operating frequency from 33 MHz to 4 MHz reduces the typical operating current of the microprocessor from 400 to approximately 100 milliamps. Nevertheless, an operating current of 100 milliamps still poses a large power drain on the battery.
A second technique for reducing power turns off the system clock during periods of inactivity. Turning off the system clock affects all circuitry on the motherboard. Consequently, the circuitry which disables the system clock must also save all pertinent information in the microprocessor and associated board logic and restore the data upon resumption of activity such that the state of the computer after resumption of the system clock will be identical to the state of the computer prior to disabling the system clock. As a result, this technique for consuming power is both costly because of the complicated circuitry and slow because of the need to store and restore the state of the computer.
Therefore, a need has arisen in the industry to provide a method and apparatus for conserving power in an electronic device which significantly reduces the power drain of the microprocessor without the need for complicated external circuitry.
SUMMARY OF THE INVENTION
In accordance with the presently claimed invention, power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing is provided. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.
In accordance with one embodiment of the presently claimed invention, power management control circuitry for coupling to a processor used to execute instructions for data processing, the power management control circuitry being external to the processor and including control circuitry and acknowledgement circuitry. The control circuitry, for coupling to the processor, provides directly to the processor a low-power-mode control signal that is: asserted in response to a detection of one or more conditions associated with having the processor enter a low power operational mode: and de-asserted in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode. The acknowledgement circuitry for coupling to the processor, receives an acknowledgement signal from the processor subsequent to the assertion of the low-power-mode control signal.
In accordance with another embodiment of the presently claimed invention, power management control circuitry for coupling to a processor used to execute instructions for data processing, the power management control circuitry being external to the processor and including control circuitry and acknowledgement circuitry. The control circuitry for coupling to the processor provides directly to the processor a power consumption control signal that is: asserted in response to a detection of one or more conditions associated with initiation of a power consumption reduction procedure: and de-asserted in response to a detection of another one or more conditions associated with termination of the power consumption reduction procedure. The acknowledgement circuitry for coupling to the processor, receives an acknowledgement signal from the processor subsequent to the assertion of the power consumption control signal.
In accordance with another embodiment of the presently claimed invention, power management control circuitry for coupling to a processor used to execute instructions for data processing, the power management control circuitry being external to the processor and including control means and acknowledgement means. The control means is for providing directly to the processor a low-power-mode control signal that is: asserted in response to a detection of one or more conditions associated with having the processor enter a low power operational mode: and de-asserted in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode. The acknowledgement means is for receiving an acknowledgement signal from the processor subsequent to the assertion of the low-power-mode control signal.
In accordance with another embodiment of the presently claimed invention, power management control circuitry for coupling to a processor used to execute instructions for data processing, the power management control circuitry being external to the processor and including control means and acknowledgement means. The control means is for providing directly to the processor a power consumption control signal that is: asserted in response to a detection of one or more conditions associated with initiation of a power consumption reduction procedure; and de-asserted in response to a detection of another one or more conditions associated with termination of the power consumption reduction procedure. The acknowledgement means is for receiving an acknowledgement signal from the processor subsequent to the assertion of the power consumption control signal.
In accordance with another embodiment of the presently claimed invention, power management control circuitry for coupling to a processor used to execute instructions for data processing, the power management control circuitry being external to the processor and including control circuitry and acknowledgement circuitry. The control circuitry, for coupling to the processor, provides directly to the processor a low-power-mode control signal that: includes first and second values: maintains the first value in response to a detection of one or more conditions associated with having the processor enter a low power operational mode: and maintains the second value in response to a detection of another one or more conditions associated with having the processor exit the low power operational mode. The acknowledgement circuitry, for coupling to the processor, receives an acknowledgement signal from the processor subsequent to an attainment of the first low-power-mode control signal value.
In accordance with another
Bluhm Mark
Garibay, Jr. Raul A.
Herubin Margaret R.
Maher Robert
Du Thuan
Lee Thomas
Vedder Price Kaufman & Kammholz P.C.
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