System for controlling operating timing of a cache memory

Details System for controlling operating timing of a cache memory System for controlling operating timing of a cache memory

1995-06-06

1998-10-27

Harrell, Robert B.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1200

Patent

active

058290214

ABSTRACT:
Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5574937 (1996-11-01), Narain

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