Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1999-02-19
2001-11-27
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S050000, C710S058000, C710S060000, C712S002000, C712S007000, C712S008000, C712S225000
Reexamination Certificate
active
06324600
ABSTRACT:
FIELD OF INVENTION
The subject of the present invention in general pertains to a new Input-Output facility design that exploits high bandwidth integrated network adapters.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, environments with servers have traditionally offered integrated network connectivity to allow direct attachments of clients such as Local Area Networks (LANs). Given the size of most servers, the number of clients usually is in the range of hundreds to thousands and the bandwidth required in the 10-100 Mbits/sec range. However, in recent years the servers have grown and the amount of data they are required to handle has grown with them. As a result, the existing I/O architectures need to be modified to support this order of magnitude increase in the bandwidth.
In addition, new Internet applications have increased the demand for improved latency. The adapters must support a larger number of users and connections to consolidate the network interfaces which are visible externally. The combination of all the above requirements presents a unique challenge to server I/O subsystems.
Furthermore, in large environments such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), there are additional requirements that the I/O subsystem must remain consistent with existing support. Applications must continue to run unmodified, and error recovery and dynamic configuration must be preserved or even improved. Sharing of I/O resources must be enabled as well as the integrity of the data being sent or received. This presents new and complex challenges that need to be resolved.
In order to achieve bandwidths which are dramatically higher and still achieve other required challenges, a new system architecture is needed.
This application is related to the following copending applications: PO9-99-013, Ser. No. 09/253,246; PO9-99014, Ser. No. 09/253,250; PO9-99-015, Ser. No. 09/253,247; PO9-99-016, Ser. No. 09/253,248; PO9-99-017, Ser. No. 09/252,712; PO9-99-018, Ser. No. 09/252,552; PO9-99-019, Ser. No. 09/252,728; PO9-99-020, Ser. No. 09/252,730; PO9-99-021, Ser. No. 09/253,101; PO9-99-023, Ser. No. 09/252,542; PO0-99-024, Ser. No. 09/253,249; PO9-99-025, Ser. No. 09/252,556; PO9-99-026, Ser. No. 09/253,993; PO9-99-027, Ser. No. 09/253,658; PO9-99-028, Ser. No. 09/252,555; PO9-99-029, Ser. No. 09/255,641; PO9-99-030, Ser. No. 09/255,640; and PO9-99-031, Ser. No. 09/252,727.
SUMMARY OF THE INVENTION
A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing mechanism having a plurality of queues capable of being shared between a plurality of independent processes running on at least one host and at least one I/O adapter. A finite-state machine (FSM) is provided in the main memory and the FSM is divided into two disjoint sets of states, one of which represents state-values processed by the host and set by the adapter, and said other set represents state-values processed by the adapter and set by said host. Using each of these set of states free-running, non-deadlocking processes are provided within the host and the adapter so that the processes sequence circularly and continuously through a vector related to the FSMs. In addition, a circular data queue is provided in the vector as to further provide a set of storage blocks within said main memory for an input or an output buffer. Using these processes and the queues, data can be moved quickly without any need to initiate any distinct input/output requests or any interruptions by the host processor for completion of each data movement.
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Brice Frank W.
Tarcza Richard P.
Wyman Leslie W.
Gonzalez Floyd A.
International Business Machines - Corporation
Lee Thomas
Neff Lily
Perveen Rehana
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