Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-09
1998-06-09
Lane, Jack A.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711160, 711 4, G06F 1200
Patent
active
057651930
ABSTRACT:
A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache. Thereafter, when the cache has fewer than a lower predetermined number of adjacent blocks free, the processor transfers block identifiers and the addresses of the blocks in the write cache to the data storage device, which allows the data storage device to retrieve the data blocks from the write cache in the order in which they are to be stored on the storage device.
REFERENCES:
patent: 4636946 (1987-01-01), Hartung et al.
patent: 5420983 (1995-05-01), Noya et al.
Noya Eric S.
Rosich Mitchell N.
Wong Jeffrey T.
Digital Equipment Corporation
Drozenski Diane C.
Fisher Arthur W.
Lane Jack A.
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