Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2002-06-28
2004-12-07
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S154000
Reexamination Certificate
active
06829691
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of computer memory management. Specifically, the present invention relates to a method and system for improving in-memory compression and decompression.
BACKGROUND ART
As the gap between hard drive access time and memory access time increases, it is increasingly desirable to locate more data in memory. This is increasingly important because the size of applications and data sets is increasing at a faster rate than the density of main memory. Furthermore, systems with multiprocessors may have many programs running simultaneously with each program having a relatively small number of pages of instructions and data in main memory. Hence, page faults may occur frequently. One way to increase the effective storage capacity of main memory is to compress its contents. However, conventional computer systems may be unable to efficiently manage the compressed data in main memory.
In typical computer operations, data can be stored in volatile memory in either compressed or uncompressed form. Therefore, for example, if a program requests data that was stored compressed, the data must be uncompressed before it is usable. Both compression and decompression may be performed in-line, for example, while in transit from a source to a destination. As computers have become faster, the speed demand on the compression/decompression process has increased enormously.
When, for example, a page of data is selected for compression or decompression, it is typically transferred from memory to a compression/decompression engine via a data bus that connects to the memory arrays. After processing in the compression/decompression engine, the data is transferred via the same bus back to memory. This requires having data, compressed and uncompressed, travelling in both directions on the same data bus. Consequently, this adds time, or latency, to the movement of the data as well as to the overall compression/decompression process. This is true even when the compression/decompression engine is located inline in the memory bus.
A number of techniques have been employed to work around the speed loss associated with both compression and decompression. For example, if the data is stored compressed in main memory and decompressed when a program requests the data, a conventional technique is to provide a cache of uncompressed data for data that is expected to be accessed with a high probability. This allows some of the data to bypass compression and avoid the latency associated with the compression/decompression processes. However, this requires additional cost for the cache and since the data is uncompressed requires more space than if stored uncompressed. Also, it is unavoidable that there will be cache misses, in which case, the compressed data must be run through the decompression engine, which as discussed is not performed efficiently in conventional systems.
Thus, a first problem with conventional methods of performing compression/decompression in main memory is failing to perform the compression/decompression process efficiently. A further problem with conventional methods is failing to take advantage of the speed of available compression engines.
DISCLOSURE OF THE INVENTION
The present invention pertains to a system for performing data compression/decompression. The system may comprise a memory controller having compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.
REFERENCES:
patent: 5606428 (1997-02-01), Hanselman
patent: 5654703 (1997-08-01), Clark, II
patent: 5864652 (1999-01-01), Murahashi
patent: 6145069 (2000-11-01), Dye
patent: 6370631 (2002-04-01), Dye
patent: 2003/0031247 (2003-02-01), Takahashi et al.
Aglietti Robert B.
Wilson Kenneth Mark
Hewlett-Packard Development L.P.
Nguyen Hiep T.
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