Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-07-25
2003-09-09
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S600000, C327S163000
Reexamination Certificate
active
06618816
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of data communications. More particularly, the invention relates to a method and apparatus for compensating the timing of data, received through a data-bus printed on a motherboard, that is sent from daughter-boards which are connected to the motherboard at different locations.
BACKGROUND OF THE INVENTION
A data bus is widely used in computer and many data communications systems. A bus is usually implemented by disposing (e.g., printing) a group of data paths on a main printed circuit board called a “motherboard” or a “backplane”. Different functional modules that are required for the operation of the system are implemented on separate dedicated printed circuit board called “daughter-boards”. Each daughter-board is connected to the motherboard via a connector or a socket, which is located at different location. Data is transmitted to, and collected from each daughter-board via the bus by assigning time slots for each data source so that no more than one data source is transmitting at a time. The data is normally exchanged over the bus at a predetermined data-rate, which is controlled by a clocking circuit. In the operation of a bus which operates at very high speeds, the exact timing of the valid data is very important for their effective operation. For example, for a bus being operated at 100 MHz, a timing error of 10 nanoseconds will result in missing the valid data entirely, and errors less than 10 nanoseconds may also be problematic. At speeds of 100 MHz and above, the time for a signal to propagate along a trace path is not negligible, and must be taken into account.
In a high speed system such as an ATM (Asynchronous Transfer Mode) switch, information is broken up into small fixed cell sizes, which are transferred at high speed. The cells typically consist of 53 bytes or octets, which is composed of a 48 byte payload, and a 5 byte header. Different switches may add local switching information in the form of a header expansion. Each unit on a bus must be prepared to transfer its data, consisting of multiple data bits, when its turn on the bus is allocated. Due to the high speed nature of an ATM system, typically a synchronization signal is sent to the unit at least one clock period in advance, so that there will be no lost time between transmissions on the bus.
One prior art method for compensation of the delay uses a Phase-Locked-Loop (PLL) in each daughter-board to set the internal timing for that daughter-board. The internal timing clock signal of each individual daughter-board (i.e., the signal which determines the timing when data should be sent) is locked to the clock signal received over the mother board. Hence, a proper delay between the received main clock signal and the internal clock can be set individually for each daughter-board by varying the loop parameters until a desired phase-shift (i.e. the desired delay) is obtained. However, using a PLL in each card is cumbersome and costly.
Gunning-Transceiver-Logic (GTL) technology (by Texas Instruments Inc., USA) is a reduced voltage high speed interface standard that provides high-speed point to point data communication at a rate of 75-133 MHz, with a theoretical speed limit of 200 MHz. These data rates are achieved through low voltage swings, and carefully controlled termination that eliminates reflections. GTL technology is however expensive, and is limited to 200 MHz, as it does not compensate for inherent timing losses.
U.S. Pat. No. 4,744,076 discloses a system having a high-speed data communication bus disposed on a motherboard with associated modules that are connected to the motherboard by using removable connections. Modules communicate with the bus through transceiver arrays which are disposed on the motherboard as close as possible to the bus. This enables the removal or the location of modules without affecting the impedance and time delay characteristics of the bus. However, the delays are constant but are not equal for each module, and therefore data sent from each modules appears on the bus with a different timing delay, or phase relationship to the master clock.
U.S. Pat. No. 5,309,035 discloses an active delay regulator that precisely measures the propagation delay of a processed clock signal and maintains a fixed phase difference with relation to an input clock signal. The delay is measured by replicating the internal path delay (i.e., a “replica loop”) and passing the input clock signal through a selected tap of a tapped delay line. However, such active regulator (an integrated circuit) is required in each individual data source which feeds a bus, and hence, the system's cost is increased.
All the methods described above have not yet provided satisfactory solutions to the problem of compensating for timing delays of data sent from daughter-boards which are connected to a motherboard at different locations, which is simple and cost effective.
It is an object of the present invention to provide a method and apparatus for compensating the timing of data sent from daughter-boards which are connected to a motherboard at different locations, to essentially equalize the timing, using no additional active component in each daughter-board.
It is another object of the present invention to provide a method and apparatus for compensating the timing of data sent from daughter-boards which are connected to a motherboard at different locations, to essentially equalize the timing, without using phase-locking techniques in each daughter-board.
Other objects and advantages of the invention will become apparent as the description proceeds.
SUMMARY OF THE INVENTION
The present invention is directed to a method for determining the timing of data arriving to a predetermined point via a data-bus from two or more data sources located at different locations along the data-bus. The timing initiated by a first clock signal, is selected from a plurality of clock signals at a frequency f, which are transmitted from a first clock generator. The total phase-shift of the data, relative to the phase of the transmitted first clock signal, is equalized for each data source. The total phase-shift is determined by transmitting a first clock signal via a separate transmission path and receiving it at the end of the path. The determined total phase-shift is then utilized for enabling the reading of the data. Equalization is carried out by generating, for each data source, a first transmission path for receiving the first clock signal and a second transmission path for transmitting data, so that the length of the sum of the first and the second transmission paths is substantially equal for each of the data sources.
Preferably, a data receiving point is determined and a plurality of data transmission paths from the receiving point to each source, forming the data-bus, is generated, where each data transmission path has a specific length. A clock signal transmission path with a unique length, is generated for each source, thereby generating a unique phase shift. The unique length of each of the clock signal transmission paths is substantially equal to the difference between a prefixed length and the specific length of the data transmission path of the each source. The first clock signal is transmitted to the source, and a first clock signal is transmitted via a dummy transmission path of a length which is substantially equal to the prefixed length, thereby shifting the phase of the second clock signal. A second clock generator, which may be part of a phase locked loop, is locked to the phase-shifted second clock signal, and the output of the locked clock generator is used to determine the timing for reading data arriving to the receiving point via the data-bus. Alternatively, a second clock signal at a frequency f
(n=2, 3, . . . ) is transmitted via the dummy transmission path, so as to shift the phase of the second clock signal. Preferably, the data sources are circuits implemented on printed circuit boards, connected to a main printed circuit board. The t
Ido Meir
Moshe Joseph
Browdy and Neimark , P.L.L.C.
Du Thuan
ECI Telecom Ltd.
LandOfFree
System for compensating delay of high-speed data by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for compensating delay of high-speed data by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for compensating delay of high-speed data by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3029176