Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-06-29
2003-02-25
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000
Reexamination Certificate
active
06526112
ABSTRACT:
BACKGROUND OF THE INVENTION
In modem digital communications systems, the function of clock and data recovery (CDR) is essential before the data can be decoded or repeated. In many systems, data in the range of 100's of megabits/sec, are time-multiplexed to form a single channel high speed data stream above a gigabit/sec. Conduits containing multiple channels of these high speed streams, such as parallel optical links, and low loss ribbon cables, have emerged. Thus, at the parallel data receiver, there is a need to provide a CDR system for multiple channels. Furthermore, there is a need to implement this CDR system on a single IC for minimal costs.
For systems where the serial channels were derived from the same clock, it is possible to use a single channel to recover the clock and retime the parallel data streams. Here, only one channel is fed into a clock extraction circuit, and the recovered clock is used to retimed the bank of parallel decision circuits (D type flip/flops)
18
as shown in FIG.
1
. The transmitter
10
in
FIG. 1
sends N parallel streams synchronous to a common clock
14
. The receiver
12
uses a recovered clock
16
extracted from a single one of the N channels to retime all N channels.
However, since the propagation through each channel has tolerance, the phase of each channel must be separately adjusted for the common clock to be used to retime the data, as the sample point of each data stream is not at its optimum. This is especially true as the distance of the conduit is increased and the tolerance gets worse. Also, each channel propagation may vary due to physical bending, etc, which requires each channel's timing to be dynamically changed.
For systems where the serial channels were derived from different clocks of the same frequency (ie different crystals of the same frequency), then each channel must have its own CDR, as shown in FIG.
2
. This is the case of a data switch or repeater. Each flip-flop
28
has a dedicated clock
24
. For the model shown in
FIG. 2
, there is a dedicated CDR circuit
26
for each of the N channels to insure that the input data stream is always sampled at its optimum point, regardless of the relative phase relationships of the various channels.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved multiple channel and data recovery system.
The present invention provides independent CDR (clock and data recovery) functions on N number of high speed parallel channels, yet only requiring one capacitor. This enables multiple independent CDR channels to be integrated onto one IC with a minimum overhead component of one capacitor.
In one embodiment, the present invention provides a multiple channel clock and data recovery system which includes N phase lock loop circuits for receiving in parallel N data channels, each of the N phase lock loop circuits including a digital phase detector and a dual-input VCO in which one VCO input is an analog input for setting the center frequency of the VCO and the other VCO input is a digital input from the respective phase detector for toggling the center frequency and wherein each phase detector compares the phase of the respective incoming data channel with that of the respective VCO output.
The system further includes a first phase lock loop circuit of the N phase lock loop circuits further including an integrator having a single capacitor, the integrator connected between the output of the first phase detector and the analog input of the respective first VCO wherein the output of the first phase detector is input to the integrator, the output of the integrator is also input to the remaining analog inputs of the other VCOs such that the remaining phase lock loop circuits are slaved to the first phase lock loop circuit.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5012494 (1991-04-01), Lai et al.
patent: 5872488 (1999-02-01), Lai
patent: 6307906 (2001-10-01), Tanji et al.
Agilent Technologie,s Inc.
Chin Stephen
Williams Lawrence
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