System for checking the acceptance of I/O request to an interfac

Details System for checking the acceptance of I/O request to an interfac System for checking the acceptance of I/O request to an interfac

1993-03-02

1997-10-28

Lee, Thomas C.

395824, 395306, 395404, 395438, 395842, G06F 1320

Patent

active

056825510

ABSTRACT:
An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus. This improves system performance over non-pended system buses and reduces the amount of hardware needed as compared to pended system buses.

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Willard "Futurebus+, An Architecture for I/O Devices," DECUS, Dec. 1991.

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