Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-10-30
2001-06-19
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S005000, C710S107000, C710S118000
Reexamination Certificate
active
06249823
ABSTRACT:
TECHNICAL FIELD
This invention relates to the field of computer systems and more particularly to a method of accessing data at high speed.
BACKGROUND
Under a typical computer system architecture, a memory controller controls access to the system memory during read and write cycles. For accessing the system memory, the memory controller processes read and write requests generated by a central processor unit (CPU), requesting data to be read from or written into a particular memory address. Upon receipt of the CPU requests, the memory controller initiates corresponding read or write cycles over a data bus, for accessing the addressed memory locations. The rate by which data is transferred, i.e., the data throughput, during each memory cycle is dependent on the bus speed as well as the width of the system's data bus and the length of a memory position, which is defined in terms of data bits, for example, 8-bit, 16-bit, or 32-bit, etc.
Each memory cycle, read or write, expends a predefined number of clock cycles, which is primarily dependent on the speed by which data can be accessed from the memory. Because the performance of a computer system is highly dependent on the data throughput, it is necessary to maximize the data transfer rate over the data bus, ideally, making it reach the full system clock speed. In addition, various techniques have been devised to increase the data throughput by minimizing the time required to access the system memory. For example, under a scheme known as data interleaving, the system memory is divided into a number of DSUs, with each DSU being addressable on a corresponding separate physical address. When accessing data, either reading or writing data, the memory bus is switched from one DSU to another after the memory controller maps the logical memory address to the physical address. In this way, data may be written to a physical address on one DSU without completing a previous write request to a physical address on another DSU.
When reading or writing data, the data bus is driven by corresponding read and write drivers. For example, the memory controller may drive the data bus during the write cycles, and a Data Storage Unit (DSU) may drive the bus during the read cycles. Physical property of the data bus, however, requires the elapse of certain amount of bus settlement time, before valid data may be presented on the data bus. In a system that utilizes a high speed data bus, the initial requirement for the elapse of the bus settlement time may prevent operating the data bus at full speed, when the bus drivers are switched. It is, however, desired to provide memory access at full speed even when switching from one driver to another.
SUMMARY OF THE INVENTION
Briefly, according the present invention, a bi-directional data bus is operated at full speed by executing a dummy cycle, when the switching of the bus drivers becomes necessary. More specifically, a method of accessing data over the bi-directional data bus drives the bi-directional bus by at least two data bus drivers. The data bus is addressed in an interleaved manner. When one or more data access requests are received, a determination is made as to whether a bus cycle, read or write, executed based on a data access request requires switching from the current bus driver to another bus driver, for example, from a data storage controller (DSC) to a DSU. If so, at least one dummy cycle is generated over the bi-directional data bus, before placing the data associated with the bus cycle on the bi-directional bus. The execution of the dummy cycle ahead of presenting valid data on the bi-directional bus allows for elapse of the initial bus settlement time associated with physical properties of the bi-directional data bus, thereby allowing the bus to operate at full speed.
According to some of the more detailed features of the present invention, a determination is made as to whether the bus drivers of one data bus were used for executing a previous bus cycle. If not, a determination is made that the change of bus drivers is necessary and the dummy cycle is executed before presenting data over the bi-directional bus. Preferably, the dummy cycle is generated at least one clock cycle prior to valid data may be presented on the bi-directional data bus. According to yet another feature of the invention, the received access requests are queued. Based on the queued accesses requests, the execution timing of the bus cycles over the bi-directional data bus is adjusted to allow for the execution of the dummy cycle, if the switching of the bus drivers becomes necessary.
In an exemplary embodiment, the data over the bi-directional data bus is exchanged between the DSC and a plurality of DSUs. Based on a received read request for data from an addressed DSU, a determination is made as to whether the addressed DSU was driving the bi-directional data bus during a previous bus cycle. The addressed DSU generates the dummy cycle over the bi-directional data bus, if it was not driving the bi-directional bus during the previous bus cycle. Also, based on a received write request for data to be written into one or more DSUs, a determination is made as to whether the DSC was driving the bi-directional data bus during a previous bus cycle. The DSC generates the dummy cycle over the bi-directional data bus, if the DSC was not driving the bi-directional bus during the previous bus cycle.
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Dahl Orvar Per
Zervens Matiss Jonas
Burns Doane Swecker & Mathis L.L.P.
Cao Chun
Lee Thomas
Telefonaktiebolaget LM Ericsson (publ)
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