System for, and method of, minimizing noise in an integrated cir

Details System for, and method of, minimizing noise in an integrated cir System for, and method of, minimizing noise in an integrated cir

1994-11-10

1997-01-21

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 21, 326 28, H03K 1716

Patent

active

055962840

ABSTRACT:
The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip. The bits from the third and fourth registers may be combined on the chip into a single word. Alternatively, the bits from the third register may be delayed on the chip by the delay of the second clock signal and combined with the bits from the fourth register. In another alternative, the combined signals may be re-registered on the chip in a fifth register in accordance with a clock signal having the delay of the second clock signal.

REFERENCES:
patent: 4857765 (1989-08-01), Cahill et al.
patent: 5194764 (1993-03-01), Yano et al.
patent: 5229657 (1993-07-01), Rackley
patent: 5326996 (1994-11-01), Yizraeli

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