Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-23
2004-03-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C382S141000, C382S144000, C382S145000, C356S237400, C356S237500
Reexamination Certificate
active
06711733
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. P2001-253110 filed on Aug. 23, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for and a method of evaluating mask patterns formed on a mask, and particularly, to a technique of correctly evaluating mask patterns formed on a mask.
2. Description of the Related Art
Semiconductor device manufacturing processes involve transferring designed patterns onto a wafer through a mask or reticle. The word “mask” in the following explanation includes both for the mask and reticle. When patterning a mask in a clean room, particles floating in the clean room may adhere to the mask to spoil the patterns formed on the mask. To avoid the problem, the patterns on the mask must be evaluated.
FIG. 1
is a block diagram showing a system for evaluating mask patterns according to a related art. A CAD data database
101
stores CAD data for semiconductor products to be formed with the use of masks. Data related to a mask is loaded from the CAD data database
101
to a critical area computation unit
102
, which computes each area on the mask where a particle of a given size causes a killer defect. A particle tester
103
tests a mask forming process and provides defect data, which is stored in a defect data database. According to the defect data, a distribution computation unit
105
computes a particle size distribution. A yield computation unit
106
computes a yield as follows:
Y=exp
(−&lgr;) (1)
where Y is the yield and &lgr; is a killer defect that is expressed as follows:
λ
=
∫
R
min
R
max
Ac
(
R
)
·
D
(
R
)
ⅆ
R
(
2
)
where Ac(R) is a critical area, D(R) is a particle size distribution, Rmax is a maximum particle size, and Rmin is a minimum particle size.
The computed yield is output from an output unit
107
. According to the output, the patterns on the mask are evaluated. This related art includes all defective patterns in the yield computation, and therefore, tends to provide a severer result than an actual condition.
SUMMARY OF THE INVENTION
An aspect of the present invention provides a system for evaluating mask patterns, including a pattern image generator configured to generate a pattern image of mask patterns to be formed on a mask, a defect generator configured to receive defect data for particles and imaginarily generate defects on the mask according to the defect data, a pattern-defect image generator configured to generate a pattern-defect image of the mask by combining the generated pattern image with the generated defects, a pattern tester configured to determine whether or not each of the defects in the pattern-defect image is allowable according to pattern rules, and a ratio computation unit configured to compute at least one of an allowable ratio and an un allowable ratio according to a determination result from the pattern tester.
Another aspect of the present invention provides a method of evaluating mask patterns, including, generating a pattern image of mask patterns to be formed on a mask, receiving data for particles, imaginarily generating defects on the mask according to the received data, and generating a pattern-defect image of the mask by combining the generated pattern image with the generated defects, determining whether or not each of the defects in the pattern-defect image is allowable according to pattern rules, and computing, according to a result of the determination, at least one of an allowable ratio and an unallowable ratio.
REFERENCES:
patent: 5917332 (1999-06-01), Chen et al.
patent: 2002/0035461 (2002-03-01), Chang et al.
patent: 2002/0057831 (2002-05-01), Hiroi et al.
patent: 2002/0181756 (2002-12-01), Shibuya et al.
patent: 2003/0058436 (2003-03-01), Ono et al.
Isomura et al., “An New Inspection Method for PSM on DUV Inspection Light Source,” IEEE, Nov. 2, 2001, pp. 64-65.*
Akeno et al., “Particle Contamination Control Technology In Electron Beam Mask Writing System for Next-Generation Mask Fabrication,” IEEE, Nov. 2, 2001, pp. 146-147.*
Charles H. Stapper, et al. “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation” IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2, May 1995, pp. 95-102.
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