System for an method of efficiently controlling memory accesses

Details System for an method of efficiently controlling memory accesses System for an method of efficiently controlling memory accesses

1997-11-18

1999-04-20

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711100, 711141, 711144, 711145, 711154, G06F 1200, G06F 1300

Patent

active

058954961

ABSTRACT:
A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

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