Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1999-03-03
2002-02-12
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
Reexamination Certificate
active
06347380
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates in general to systems for processing audio data and in particular to an audio system or sub-system for adjusting clock rate to avoid audio data overflow and underrun.
When audio data is transferred between systems, the audio data is typically written into a buffer at a writing speed and read at a rate of reading during the transfer. If the audio data is read from the buffer at a rate slower than the writing speed, the audio data in the buffer will overflow, resulting in loss of data. On the other hand, if the audio data is read at a rate faster than the writing speed, buffer underrun will occur, resulting in the wrong data being read. If the audio data read from the buffer is played back through a speaker, the corruption of audio data due to the memory overflow or underrun will be immediately noticed by the listener and is undesirable.
The Universal Serial Bus (“USB”) is intended as a bi-directional, isochronous, low-cost, dynamically attachable serial interface to promote easy personal computer peripheral expansion and provide full support for real-time voice, audio and compressed video data. The USB specification is a proposed standard promulgated by a group of computer companies including Compaq Computer Corporation, Digital Equipment Corporation, IBM Corporation, Intel Corporation, MicroSoft Corporation and Northern Telecom. The USB Specification, Compaq et al. Revision 0.9, Mar. 31, 1995 is hereby incorporated by reference.
Where the audio data is transferred from a host computer through an isochronous bus such as the USB to a peripheral such as a speaker sub-system, the host computer clock should be operated at the same rate as the speaker sub-system. However, due to the inaccuracy of the components used in the host system and in the audio sub-system, the two operating frequencies will be different. No matter how small the difference is, the cumulative effect of the difference over time will cause memory overflow or underrun at the audio sub-system memory. Such audio data overflow or underrun may cause problems when the audio data is converted by an audio CODEC and played back through a loud speaker. Even after synchronizing clock rates so that such audio data overflow or underrun does not occur at the host system memory, audio data overflow or underrun can still occur at the audio sub-system memory, such as at a FIFO supplying audio data to a audio coder/decoder (“CODEC”) where the digital audio data is converted to audio analog data which is then sent directly to the speaker for playback.
SUMMARY OF THE INVENTION
Audio data overflow or underrun is avoided by adjusting the rate of reading audio data from the memory. A phase locked loop generates a clock signal for controlling the rate of reading or writing the audio data from or into the memory. A condition that will cause memory overflow or underrun is detected. The phase locked loop is caused to adjust the clock signal in response to a detected condition that will cause memory overflow or underrun. The clock signal is adjusted so that memory overflow and underrun is avoided.
Audio data overflow and underrun can also be avoided in an audio sub-system memory that supplies audio data to the audio CODEC by adjusting the rate of reading or writing audio data from or into the audio sub-system memory. The audio CODEC performs analog to digital and digital to analog conversions of audio data supplied to a speaker and received from a microphone. A condition that will cause audio sub-system memory overflow or underrun is detected and the rate of reading or writing audio data from or into the memory is adjusted in response to such condition to avoid memory overflow and underrun.
REFERENCES:
patent: 5778218 (1998-07-01), Gulick
patent: 6055216 (2000-04-01), Shintani
“Universal Serial Bus Specification,” Compaq, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, Northern Telecom, Revision 0.9, Mar. 31, 1995, pp. ii-120.
Cai Jiwen
Chang Steve
Heckler Thomas M.
Hsue James S.
KC Technology, Inc.
LandOfFree
System for adjusting clock rate to avoid audio data overflow... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System for adjusting clock rate to avoid audio data overflow..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for adjusting clock rate to avoid audio data overflow... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2953753