System for accessing dynamic random access memory where the logi

Details System for accessing dynamic random access memory where the logi System for accessing dynamic random access memory where the logi

1996-06-28

1998-12-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711154, 711167, G06F 1300

Patent

active

058453121

ABSTRACT:
A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.

REFERENCES:
patent: 4414664 (1983-11-01), Greenwood
patent: 5608688 (1997-03-01), Park
patent: 5682354 (1997-10-01), Manning
Jim Handy, The Cache Memory Book, Academic Press, Inc., 1993, Section 1.3.1 and Glossary, 1993.
Yamashita et al., "Integrated Memory Array Processor LSI with 64 Processing Elements and 2Mb SRAM", IEEE International Solid-State Circuits Conference, vol. 37, FA15.2, (1994) pp. 260-261.
Gwennap, "Intel's P6 Uses Decoupled Superscalar Design: Next Generation of x86 Integrates L2 Cache in Package with CPU", Microprocessor Report, (1995) pp. 9-15.

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