System controller using plural CPU's

Details System controller using plural CPU's System controller using plural CPU's

2006-03-21

2006-03-21

Shin, Christopher (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S048000, C710S059000, C710S100000, C712S029000, C712S225000, C712S245000

Reexamination Certificate

active

07016984

ABSTRACT:
In a system controller in which a plurality of CPUs connected through a shared bus are connected to a plurality of memory units or IO devices through a bus for separate transfer of a read instruction from a read data return, a CPU which has issued a new instruction and the destination of the instruction, and a CPU which has issued an instruction being suspended and the destination of the instruction are held, the issue order of the return data and the transfer instruction is maintained based on the held contents in a read time, and transfers, which are first serialized and transferred through the shared bus, are issued in parallel using a plurality of connection paths. Thus, the performance of the system controller using a plurality of CPUs can be successfully improved.

REFERENCES:
patent: 4958273 (1990-09-01), Anderson et al.
patent: 5890007 (1999-03-01), Zinguuzi
patent: 6178493 (2001-01-01), Lenk et al.
patent: 6611908 (2003-08-01), Lentz et al.
patent: 2003/0037224 (2003-02-01), Oehler et al.
patent: 2003/0115392 (2003-06-01), Fujiwara et al.

Affiliated with

Also associated with

Rating

System controller using plural CPU's does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System controller using plural CPU's, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System controller using plural CPU's will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3536292