System controller and cache control method

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S156000, C711S167000

Reexamination Certificate

active

07979644

ABSTRACT:
A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers.

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International Search Report mailed Sep. 12, 2006 in connection with International Application No. PCT/JP2006/303789.

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