System carrier for a semiconductor chip having a lead frame

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – Small lead frame for connecting a large lead frame to a...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S666000, C257S668000, C257S670000, C257S671000, C257S674000, C257S676000, C257S690000, C257S696000

Reexamination Certificate

active

06563201

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a system carrier or substrate for a semiconductor chip with a conductor frame.
Such system substrates are used in semiconductor technology for retaining flat conductors of various sizes at predetermined positions on longitudinal webs and transverse webs of a conductor frame. Small-area flat conductors that extend from the webs are provided on their free ends with contact terminal faces. These contact terminal faces are connected to microscopically small contact terminals, that is, contact terminals that are perceptible only under a light microscope, on the semiconductor chip, in particular via bonding wires using wire bonding technology or via solder bumps using flip-chip technology. Large-area flat conductors are provided for carrying current or are provided as volumetric balancing pieces. Between the large-area flat conductors and the webs of the conductor frame, there are connecting webs that have bent areas.
In this connection, the term “large area” pertaining to the flat conductors means a multiple of the area of a small-area, elongated signal flat conductor. Large-area flat conductors can for example have a trapezoidal or triangular shape, depending on the remaining faces between the conductor frame and the signal flat conductors. Large-area flat conductors have a tendency, when the system substrate is encapsulated in a plastic casting composition, to change their predetermined position and to threaten bonding connections.
SUMMARY OF THE INVENTION
The object of the invention is to avoid breakage of bonding connections upon encapsulation, by means of a suitable system substrate.
According to the invention, the bent areas in the connecting webs, for large-area flat conductors, are provided at different spacings from the webs of the conductor frame, so that no coincident pivot axis for the bent areas about which the large-area flat conductors could swivel elastically, shift, or vibrate can form, since the bent areas are disposed at different spacings from the webs of the conductor frame. This also fixes the three-dimensional position of the large-area flat conductors, so that their free ends can no longer swing unhindered. Overall, without having to introduce additional bent areas in the connecting webs and without having to use more dimensionally stable materials, the rigidity of the large-area flat conductors is increased.
In one embodiment of the invention, the large-area flat conductors have oblong-slotlike openings, which are dimensioned such that the remaining flat conductor material is given a width adapted to the signal flat conductors. This embodiment has the advantage that in the remaining trapezoidal or large-area faces between the webs and the many signal flat conductors, the shrinkage of the plastic casting composition in the injection molding operation for a plastic semiconductor housing is made uniform in all regions of the system substrate, and thus sagging and rejection of the plastic housing for a semiconductor chip is reduced.
To that end, in a Cartesian coordinate system the conductor frame extends in the X-Y direction, and the bent areas are disposed in the Z directions. The large-area flat conductors are located in a plane that is offset in the Z direction from the plane of the signal flat conductors. This offset is first for historical reasons and corresponds to the applicable thickness of the semiconductor chip, so that the large-area flat conductors can be connected to the underside of the semiconductor chip. However, since for the above reasons this connectability is no longer necessary for modern semiconductor chips or can no longer be achieved, these bent areas of the connecting webs between large-area flat conductors and webs of the conductor frame serve to dispose the flat conductors in an offset plane, to lend improved stability to the plastic semiconductor housing.
Because of the increased rigidity from the offset arrangement of the bent areas in the connecting webs, the vibrations of the large-area flat conductors are reduced to such an extent that the aforementioned negative effects no longer occur, and the bonding wire connections are not threatened. In the injection molding of the plastic housing, a stabler state of the system substrate is thus achieved.
In a further embodiment of the invention, a single large-area flat conductor has two connecting webs to one web of the conductor frame, and one of the connecting webs has its bent areas in the Z direction at a greater spacing from the web of the conductor frame than the other. This is advantageously the simplest embodiment of the present invention.
In a further embodiment, a single large-area flat conductor has three connecting webs, and a middle connecting web has its bent areas in the Z direction at a greater spacing from the web of the conductor frame than the other two connecting webs. Compared with the simplest embodiment, referred to above, this embodiment has the additional advantage that with three connecting webs and with corresponding bent areas offset in spacing, the rigidity and positional accuracy of the large-area flat conductor can be increased considerably; the middle connecting web can protrude with its bent areas as far as the center of the large-area flat conductor.
The middle connecting web of a large-area flat conductor with three connecting webs can, in a further embodiment, have a bent area in the Z direction at a lesser spacing from the web of the conductor frame than the other two connecting webs. In that case, the peripheral zones of the large-area flat conductor are shortened considerably, and the middle region of the flat conductor is lengthened accordingly, so that a stable position of the large-area flat conductor can be assured.
In a further embodiment, a single large-area flat conductor can have a plurality of connecting webs to one web, with two different spacings of the bent area of the connecting webs from the web of the conductor frame; the bent areas are disposed at alternating spacings from the web of the conductor frame. This embodiment of the invention should be used particularly whenever area of the large-area flat conductor becomes greater because of increasing chip sizes and increasing signal conductor tracks. The alternating arrangement of the spacings of the bent areas of the connecting webs furthermore has the advantage that the large-area flat conductor is stiffened at a plurality of points.
In a further embodiment of the invention, in a large-area flat conductor with a plurality of connecting webs to one web of the conductor frame, the bent areas are disposed in groups with regard to the spacings, and the group of connecting webs having the greatest spacing of the bent areas from the web are disposed in the region of the greatest length of the large-area flat conductor. It is thus advantageously assured that the greatest length of the large-area flat conductor is shortened, since the connecting webs are lengthened accordingly, so that the bent areas will attain a greater spacing from the web of the conductor frame. Compared with an alternating arrangement of the spacings of the bent areas from the transverse web, this offers enhanced stability, especially for the longest length of the large-area flat conductor.
With a further embodiment of the invention, the bent areas can be staggered with regard to the spacings from the web; the connecting web with the greatest spacing of the bent areas from the web of the semiconductor chip is disposed in the region of the longest length of the large-area flat conductor. Although the tool for countersinking the bent areas in a staggered way is more complex in structure than if only two different magnitudes of spacing had to be taken into account, nevertheless the staggering of the spacings of the bent areas in the connecting webs offers the greatest possible rigidity for the large-area flat conductors and thus the greatest possible stability of the substrate system upon encapsulation of an electronic semiconductor circuit in a pl

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System carrier for a semiconductor chip having a lead frame does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System carrier for a semiconductor chip having a lead frame, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System carrier for a semiconductor chip having a lead frame will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3036732

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.