System bus read data transfers with data ordering control bits

Details System bus read data transfers with data ordering control bits System bus read data transfers with data ordering control bits

2007-12-11

2007-12-11

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S128000, C711S144000, C711S003000, C710S066000, C710S065000, C710S001000

Reexamination Certificate

active

11041711

ABSTRACT:
A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.

REFERENCES:
patent: 5781923 (1998-07-01), Hunt
patent: 5848436 (1998-12-01), Sartorius et al.
patent: 5978841 (1999-11-01), Berger
U.S. Appl. No. 09/436,419, Related Co-Pending Application: Ravi K. Arimilli, et al., filed Nov. 9, 1999.
U.S. Appl. No. 09/436,420, Related Co-Pending Application: Arimilli, et al., filed Nov. 9, 1999.
U.S. Appl. No. 09/436,422, Related Co-Pending Application: Arimilli, et al., filed Nov. 9, 1999.

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