Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-11-09
2003-03-18
Nguyen, T. V. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S137000, C711S145000
Reexamination Certificate
active
06535957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and in particular to a method and system for transmitting data in a selected (preferred) order. Still more particularly, the present invention relates to a method and system for transmitting data in a selected order wherein the order selected is based on the system bus utilization/loading and is encoded in selected order bits.
2. Description of the Related Art
In conventional symmetric multiprocessor (SMP) data processing systems, all of the processors are generally identical. The processors all utilize common instruction sets and communication protocols, have similar hardware architectures, and are generally provided with similar memory hierarchies. For example, a conventional SMP data processing system may comprise a system memory, a plurality of processing elements that each include a processor and one or more levels of cache memory and a system bus coupling the processing elements to each other and to the system memory.
Conventional SMP data processing system processors have a number of execution units. Superscalar multiprocessors typically have more than one of each execution unit. They typically have two floating point units (FPUs), two fixed point units (FXUs) and two load/store units (LSUs). The processors are designed for high frequency and their corresponding internal caches are typically very small in order to operate with the high frequency processor. In part due to their relatively small size, these internal caches sustain a large number of cache misses during requests for data. Data is thus stored in lower level (L2 or L3, etc.) caches to maximize processing speed. The processors typically send multiple load requests simultaneously or within close proximity to each other. This is particularly true in superscalar processors with multiple LSUs.
A typical cache memory, for example, stores the contents of frequently accessed random access memory (RAM) locations and the addresses where these data items are stored. When the microprocessor references an address in memory, the cache memory checks to see whether it holds that address. If the cache memory does hold the address, the data is returned to the microprocessor; if it does not, a regular memory access occurs.
In an SMP system with processors running at very high frequencies, system performance can be highly sensitive to main memory latency. One method to reduce latency is to use an L3 cache which may be shared by multiple CPUs in the system. Since many of today's CPUs have fairly large L2 caches, the shared cache (L3 cache) must be very large to have a marked impact on system performance.
In order to increase the speed of access to data stored within the main memory, modern data-processing systems generally maintain the most recently used data in the cache memory. The cache memory has multiple cache lines, with several bytes per cache line for storing information in contiguous addresses within the main memory. Each cache line essentially comprises a boundary between blocks of storage that map to a specific area in the cache memory or high-speed buffer. In addition, each cache line has an associated “tag” that typically identifies a partial address of a corresponding page of the main memory. Because the information within cache may come from different pages of the main memory, the tag provides a convenient way to identify which page of the main memory a cache line belongs.
In a typical cache memory implementation, information is stored in one or several memory arrays. In addition, the corresponding tags for each cache line are stored in a structure known as a directory or tag array. Usually, an additional structure, called a translation lookaside buffer (TLB), is also utilized to facilitate the translation of a virtual address to a real address during a cache memory access. Cache memory access thus involves reading out a line of the cache and its associated tag. The real address from a translation array is then compared with the real address from the tag array. If these real addresses are identical, then the line in the cache that was read out is the desired line, based on the effective or virtual address calculated by the algorithm in use.
As indicated above, data stored in a data cache or memory are stored on cache lines. A typical cache line for example, may be 64 bytes and represented in eight 8×8 byte partial cache lines (i.e., 8 beats of 8 bytes).
An exemplary cache line (block) includes an address tag field, a state bit field, an inclusivity bit field, and a value field for storing the actual instruction or data. The state bit field and inclusivity bit fields are used to maintain cache coherency in a multi-processor computer system (indicate the validity of the value stored in the cache). The address tag is a subset of the full address of the corresponding memory block. A compare match of an incoming address with one of the tags within the address tag field indicates a cache “hit.” The collection of all of the address tags in a cache (and sometimes the state bit and inclusivity bit fields) is referred to as a directory, and the collection of all of the value fields is the cache entry array.
In order to access a byte in a cache memory with an effective or virtual address, the line portion (mid-order bits) of the effective or virtual address is utilized to select a cache line from the memory array, along with a corresponding tag from the directory or tag array. The byte portion (low-order bits) of the effective or virtual address is then utilized to choose the indicated byte from the selected cache line. At the same time, the page portion (high-order bits) of the effective address is translated via the segment register or segment lookaside buffer and TLB to determine a real page number. If the real page number obtained by this translation matches the real address tag stored within the directory, then the data read from the selected cache line is the data actually sought by the program. If the real address tag and translated real page number do not agree, a cache “miss” occurs, meaning that the requested data was not stored in the cache memory. Accordingly, the requested data must be retrieved from the main memory or elsewhere within the memory hierarchy.
Both address translation and cache access involve comparison of a value read from one array with another value read from a different array. In the case of address translation, the virtual segment identifier associated with a given effective address and stored in a segment register or segment lookaside buffer is compared with the virtual address stored as part of an entry in the translation lookaside buffer. Similarly, the translated real page number is compared with the real page number read from the cache tag array to determine whether the accessed line in the cache is the required real page number.
As the need for processor efficiency increases, the retrieval order of data from cache lines becomes increasingly important. Cache lines typically contain several data values stored as words, double words, octa-words, etc. Particular data values within a cache line may be considered critical (i.e., more important to processing efficiency than the other values or desired to be retrieved in a particular order) by a processor. Cache access and data retrieval is initiated with processor load requests which are transmitted from the processor to the L1 cache first.
Load requests are comprised primarily of read addresses, which identify a location of the required data. When a read address misses on the internal memory caches (L1), they are sent over the system bus to the lower level caches (L2, L3, etc.). The addresses are sent over the system buses as snoop requests. These snoop requests are broadcasted over the system bus to every component which is connected to the system bus. The components which actively snoop the system bus, particularly the lower level caches, look up in their cache directory to see if the requested address is present in t
Arimilli Ravi Kumar
Chung Vicente Enrique
Guthrie Guy Lynn
Joyner Jody Bern
Bracewell & Patterson L.L.P.
Nguyen T. V.
Salys Casimer K.
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