System bus arbitrator for facilitating multiple transactions in

Details System bus arbitrator for facilitating multiple transactions in System bus arbitrator for facilitating multiple transactions in

1998-04-13

2000-07-04

Myers, Paul R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

G06F 1300

Patent

active

060852712

ABSTRACT:
A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.

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