System board and impedance control method thereof

Details System board and impedance control method thereof System board and impedance control method thereof

2001-04-13

2003-09-16

Pascal, Robert (Department: 2817)

Wave transmission lines and networks

Coupling networks

With impedance matching

C333S125000, C326S030000

Reexamination Certificate

active

06621371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control apparatus and a system board comprising modules (or devices) controlled by the control apparatus, and more particularly, a system board and an impedance control method of the board for preventing the distortion of signals transmitted between modules (or devices) controlled by the control apparatus.
2. Description of the Related Art
In general, a system such as a computer comprises a control apparatus or controller and modules controlled by the controller. A typical example is a memory subsystem comprising memory modules and a memory controller. But, as data processing speed of a system increases and the amount of data to process grows, the number of modules to be plugged into a system board increases.
A system such as a computer comprises a mother board, where modules are plugged into connectors installed in the mother board. The number of modules plugged into the mother board increases according to the improvement of system performance, and an impedance of a signal line which the mother board itself has varies as modules are plugged into the mother board. This is because a unit capacitance of a transmission line varies by parasitic capacitance of the module.
In general, the distances between connectors installed in a mother board of a computer system are equal, and modules installed in these connectors are controlled by one control apparatus. Therefore, in the conventional system board, there is a great difference between a characteristic impedance of a signal line from a control apparatus to a first connector and a characteristic impedance of a signal line connected to other connectors in case those modules are plugged into the connectors. That is, the characteristic impedance of the signal line from the control apparatus to the first connector is larger than the characteristic impedance of the signal line connected to other connectors in case those modules are plugged into the connectors.
In this case, a signal distortion phenomenon can occur by a reflection due to the impedance difference in the process of signal transmission through the signal line.
A conventional system board will be described as follows with reference to the accompanying drawings.
FIG. 1
is a block diagram showing a configuration of a mother board of a conventional computer system, which comprises a control apparatus
10
, and n connectors CON
1
, CON
2
, CON
3
, . . . CONn. The n connectors CON
1
, CON
2
, CON
3
, . . . and CONn shown in
FIG. 1
are installed in a mother board in order to plug n modules (not shown), and the control apparatus is installed in the mother board directly.
In
FIG. 1
, a signal line to transmit data DQ and strobe signal is arranged between the control apparatus
10
and the n connectors CON
1
, CON
2
, CON
3
, . . . and CONn. The length of a signal line from the control apparatus
10
to a first connector CON
1
is l0, and the length of a signal line between connectors CON
1
, CON
2
, CON
3
, . . . and CONn is l
0
.
A mother board shown in
FIG. 1
inputs and outputs data between the control apparatus
10
and a corresponding memory module plugged into the n connectors CON
1
, CON
2
, CON
3
, . . . and CONn in response to a strobe signal being output from the control apparatus
10
.
Unlike the configuration shown in
FIG. 1
, the control apparatus
10
can be plugged into the mother board through a connector like modules, not being plugged into the mother board directly, and also, modules can be plugged into the mother board directly, not through n connectors CON
1
, CON
2
, CON
3
, . . . and CONn. That is, an impedance control method of a system board of the present invention to be described below is applied not only in the case of the embodiment shown in the above-mentioned
FIG. 1
FIG. 2
illustrates a configuration modeling the block diagram shown in
FIG. 1
, which models the configuration where n modules M
1
, M
2
, M
3
, . . . and Mn are plugged into n connectors CON
1
, CON
2
, CON
3
, . . . and CONn, and k memory devices D
1
, . . . and Dk are loaded in each of n modules M
1
, M
2
, M
3
, . . . and Mn.
In
FIG. 2
, a serially-connected package P
1
and an input driver IB
1
and an output driver OB
1
illustrate a control apparatus
10
. A serially-connected stub resistor Rs and k memory devices D
1
, . . . and Dk illustrate each of modules M
1
, M
2
, M
3
, . . . and Mn, and serially-connected packages P
21
, . . . and P
2
k
and input/output drivers IB
21
, OB
21
, . . . and IB
2
k
, OB
2
k
illustrate each of k memory devices D
1
, . . . and Dk. l
0
and l
0
indicate the length of signal lines on the mother board; l
0
indicates the length of a signal line from a resistor Rm to a first connector CON
1
, and l
1
indicates the length of a signal line from the first connector CON
1
to a nth connector CONn.
RT
1
and VT
1
indicate a terminal resistor and a terminal voltage, respectively, to terminate a signal transmitted from one of modules M
1
, M
2
, M
3
, . . . and Mn to the control apparatus
10
, and RT
2
and VT
2
indicate a terminal resistor and a terminal voltage, respectively, to terminate a signal transmitted from the control apparatus to the modules M
1
, M
2
, M
3
, . . . and Mn, respectively. That is, a signal transmitted from one of the modules M
1
, M
2
, M
3
, . . . and Mn to the control apparatus
10
is terminated by the terminal resistor RT
1
and the terminal voltage VT
1
having a specific voltage difference, the signal transmitted from the control apparatus
10
to the modules M
1
, M
2
, M
3
, . . . and Mn is terminated by the terminal resistor RT
2
and the terminal voltage VT
2
having a specific voltage difference.
The drawings of FIG.
1
and
FIG. 2
are disclosed in 1998 Symposium on VLSI Circuits Digest of Technical Papers with a title of “5G Byte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM”.
Looking at the length of a signal line of a mother board of the conventional computer system as shown in FIG.
1
and
FIG. 2
, the length of signal lines between n connectors CON
1
, CON
2
, CON
3
, . . . and CONn are equal, except the length of a signal line from the control apparatus
10
to the first connector CON
1
. Then, the variation of a characteristic impedance of a signal line in case that the signal is transmitted from the control apparatus
10
to the modules M
1
, M
2
, M
3
, . . . and Mn is as follows, by calculating the characteristic impedance of the signal line in case that the modules M
1
, M
2
, M
3
, . . . and Mn are not plugged into the mother board of the computer system and the characteristic impedance of the signal line in case that the modules M
1
, M
2
, M
3
, . . . and Mn are plugged into the mother board as shown in FIG.
1
.
The characteristic impedance Z in the case in which the modules M
1
, M
2
, M
3
, . . . and Mn are not plugged into the connectors CON
1
, CON
2
, CON
3
, . . . and CONn of the mother board of the computer system as shown in
FIG. 1
, can be described as the following equation (1), if an inductance per unit length of the signal line of the mother board are L and C, respectively.
Z
=
L
C
(
1
)
On the other hand, a characteristic impedance Z′ of the signal line in case that the modules M
1
, M
2
, M
3
, . . . and Mn are plugged into the connectors CON
1
, CON
2
, CON
3
, . . . and CONn of the mother board can be described as the following equation (2), if a parasitic capacitance of each of the connectors CON
1
, CON
2
, CON
3
, . . . and CONn is Cc and the distance between connectors is l1.
Z
′
=
L
C
+
Cc
11
(
2
)
As known from equations (1) and (2), because the modules M
1
, M
2
, M
3
, . . . and Mn are plugged into the connectors CON
1
, CON
2
, CON
3
, . . . and CONn, the magnitude of a denominator of the characteristic impedance Z′ becomes larger than the magnitude of a denominator of the characteristic impedance Z of the signal line, and thus the magnitude of the characteristic impedance Z′ decreases. As a result, the characteristic impeda

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