Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
2000-08-03
2003-12-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
C710S052000, C710S065000, C711S100000, C712S225000
Reexamination Certificate
active
06671747
ABSTRACT:
FIELD OF INVENTION
This invention pertains generally to the field of computer system device write operations and more particularly to system, apparatus, method, and computer program for performing multiple write operations of data and/or commands from a processor or other command or data source to a hardware device in a manner that the processor's or executing procedure's intended order of receipt by the device is preserved.
BACKGROUND OF THE INVENTION
Heretofore, programs and/or processes that generate data and/or commands under programmatic control, such as in a device driver program, applications program, or the like, have frequently been forced to employ a conservative memory management strategy when the target for the command or data is a hardware device, so that the intended order of receipt of data or commands by the device is assured. Hardware devices (such as printer devices, modems, graphics processors, and the like, to name a few) may be problematic because such devices do or may respond immediately upon receipt of the particular command or data item, and may not typically wait to receive all of the data or commands that will be sent from a processor, microprocessor, or computing system. Waiting to receive all the data or comments would provide an opportunity to sort the data or commands into the temporal order intended by the application executing on the computing system and being communicated to the hardware device. In some instances, it would not even be possible for the hardware device to reconstruct the intended time order as insufficient information is provided to the device respective of the intended temporal order. Often the temporal order is an indicator of the identity of particular data or commands, so that out-of-order receipt causes the data on command to be interpreted by the receiving device in an unintended manner. A memory on the other hand, can typically wait for all of the anticipated data and/or commands to arrive before accessing it, and if required, restore it to the proper temporal order, before accessing it.
While this approach may be applicable to some hardware devices, for such hardware devices, this conservative approach (sometimes referred to as sequential, in-order, or strong memory management) unfortunately results in some degradation in performance, typically manifested as reduction of available bandwidth. On the other hand, if a less conservative memory management strategy (sometimes referred to as out-of-order or weak memory management) could be employed for hardware devices, then performance sacrifices could be minimized.
In the embodiment of a computer system
102
illustrated in
FIG. 1
, level 1 (L1) cache memory
252
is coupled to processor
250
via a bus
258
, and level 2 (L2) cache
254
is coupled to processor
250
by bus
256
. Bridge circuits as are known in the art may be interposed between the structure. The inventive structure and method described hereinafter are also applicable to multi-processor environments and multi-processor computers; however, we use the term processor or CPU generally to refer to single processor environments, dual-processor environments, and other multiple processor environments and computer or information processing systems. Caches
252
,
254
serve to provide temporary memory storage for processing that may or will be needed for near-term execution cycles within the processor. For non-short term storage the system memory
278
would generally be used rather than caches
252
,
254
. The use of a cache memory in association with a processor
250
in a computing system
102
system of the type illustrated in
FIG. 1
is known, and not described further.
System memory
278
may, for example comprise solid-state addressable Random Access Memory (RAM) of which there are many conventional varieties, and is used to store commands, addresses, data, and procedures for use by the computer system
102
. System memory
278
may for example, store all, or portions of hardware drivers for operating devices
290
,
292
,
110
and in the inventive graphic processor
210
described above.
Processor
250
is also connected to a write buffer
204
by address bus (ADDR)
260
, and data bus (DAT)
262
. Write buffer
204
is interposed between processor
250
and memory controller
268
which controls the flow of command/control/address/data between write buffer
204
and either system memory
278
or devices attached to one or more peripheral busses, such as a graphics processor
110
on a Advanced Graphics Processor (AGP) Bus
286
, or Device “A”
290
or Device “B”
292
on a Personal Computer Interface (PCI) Bus
288
. Devices “A” or “B” could for example, comprise printers, cameras or other sensors, modems, secondary processors, other graphics processors, and any other conventionally known computer device or system.
It should also be understood that such devices need not be PCI Bus compatible devices, but may also include for example AGP Bus, SCSI, ISA, Universal Serial Bus (USB), fibre channel, fire wire, or other compatible devices, and that such devices may be configured to operate internal to a computer housing such as within a slot on the computer motherboard, or as external peripheral devices connected by cable or wireless connection. The types of computer system devices or hardware devices include the types used for IBM compatible personal computers (PCs), MacIntosh PowerMac, Power PC, iMAC, and the like computers made by Apple Computer, workstations (such as, for example, the Sun Microsystems, SPARC workstation), specialized microprocessors, or even mainframe type computer systems.
Processor
250
may be of the type having internal or external caches with or without chipsets connecting to I/O or graphics processor buses, or where multiple processors are connected tightly or distributively sharing or not storing memory. Such microprocessor may for example implement RISC, CISC, VWIS, or other instruction sets and may support speculative execution, or the like advanced processing concepts. For example, the Intel Pentium, Intel Pentium II, Intel Pentium III, Intel Merced, ARM, Advanced Micro Devices K6, Advanced Micro Devices K6-3 or K7, Compaq Alpha, IBM Power PC, Sun Microsystems SPARC, Silicon Graphics (SGI) MIPS or any other processor, microprocessor or CPU may be used. Systems may also include a plurality of the same or different processors.
Of particular interest are the Intel Pentium® II & III microprocessors (and other successor processors that utilize the functionality) which utilize fast writes and uncached write combine operations. Other modem processors also generate results out-of-order, for example as a result of speculative execution, branch operations, parallel processing, and the like. Generally, uncached write operations refer to program-generated data written directly to system memory, rather than to an L1 or L2 cache. This may also be called uncached speculative write combining (USWC), and part of the address space of the processor may be specified to be of the UWSC type. The advantage of USWC-type memory is the ability to receive out-of-order write operations shortly after the processor generates a write operation, avoiding synchronization with other write operations, thereby increasing processing throughput.
Write buffer
204
is of conventional type and may for example be implemented with a static RAM. Usually, processor
250
, L1 cache
252
, and write buffer
204
are formed on a single common substrate within a single chip. Write buffer
204
may be envisioned as including a plurality (for example “n”) of cache lines
205
for temporarily storing command/address/data sent from processor
250
to memory controller
268
and ultimately to either system memory
278
or other input/output or peripheral devices, including for example device “A”
290
, device “B”
292
, or hardware device
110
.
In the embodiment illustrated in
FIG. 1
, the hardware device includes a hardware device processor
134
(such as a graphics pipeline of a graphics processor), and a First-In-F
Benkual Jack
Duluk, Jr. Jerome F.
Ho Thomas Y.
Ananian R. Michael
Apple Computer Inc.
Dorsey & Whitney LLP
Gaffin Jeffrey
Mai Rijue
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