Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-10-23
2007-10-23
Detschel, Fred W (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S200000
Reexamination Certificate
active
11012006
ABSTRACT:
A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.
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Reed David G.
Simeral Brad W.
Surgutchik Roman
Treichler Sean Jeffrey
Cooley Godward Kronish LLP
Detschel Fred W
NVIDIA Corporation
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