Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-07-03
2007-07-03
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S220000, C711S165000
Reexamination Certificate
active
11012025
ABSTRACT:
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.
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Reed David G.
Simeral Brad W.
Surgutchik Roman
Treichler Sean Jeffrey
Bragdon Reginald
Cooley Godward Kronish LLP
Mackall Larry T
NVIDIA Corporation
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