System, apparatus and method for avoiding page conflicts by...

Details System, apparatus and method for avoiding page conflicts by... System, apparatus and method for avoiding page conflicts by...

2007-09-25

2007-09-25

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S006000, C711S200000, C711S205000, C711S206000

Reexamination Certificate

active

11012007

ABSTRACT:
A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.

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patent: 6745277 (2004-06-01), Lee et al.
patent: 6772315 (2004-08-01), Perego
INTEL, “Intel® 820 Chipset: 82820 Memory Controller Hub (MCH),” Datasheet,Copyright © Intel Corporation, Nov. 1999, Document Number: 290630-001, pp. 1-157.
INTEL, “Intel® 850 Chipset: 82850 Memory Controller Hub (MCH),” Datasheet,Copyright © Intel Corporation, Nov. 2000, Document Number: 290691-001, pp. 1-144.

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