System and technique to reduce cycle time by performing...

Details System and technique to reduce cycle time by performing... System and technique to reduce cycle time by performing...

2006-08-29

2006-08-29

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S102000, C711S103000, C711S104000, C711S105000, C711S167000, C365S233100, C365S233500, C345S534000, C345S535000, C713S502000

Reexamination Certificate

active

07099989

ABSTRACT:
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.

REFERENCES:
patent: 5761139 (1998-06-01), Shibata et al.
patent: 5805873 (1998-09-01), Roy
patent: 5889727 (1999-03-01), Hsu et al.
patent: 6125421 (2000-09-01), Roy
patent: 6615331 (2003-09-01), Morzano

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