Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-22
2001-06-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06247165
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to techniques for producing gate-level and structural descriptions used in a computer controlled EDA system for integrated circuit (IC) design.
BACKGROUND OF THE INVENTION
An electronic design automation (EDA) system is a form of computer aided design (CAD) system and is used for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on library primitives. The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific library. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The netlist may then be used to generate a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
FIG. 1
illustrates a typical design flow
10
for the design of integrated circuits (e.g., ASIC, microprocessors, microcontrollers, etc.). This IC design flow
10
requires several equivalent descriptions of the design library that are used as input to different CAD tools. In the prior art system
10
, a set of hand-coded descriptions of low-level design cells is referred to as a “library.” For instance, an implementation library
12
and a reference library
22
are shown. Because these libraries
12
and
22
are hand-coded, significant effort is expended in creating these libraries
12
and
22
, verifying their equivalence, and maintaining multiple sets of descriptions across various versions of the same IC design. Hand-coding is not only time consuming, but is often error-prone and leads to incomplete modeling. It would be advantageous to reduce the effort required to generate a library within an IC design process to thereby reduce IC design time, reduce cost and increase IC design accuracy.
In typical CAD design flows, the implementation library
12
is the “golden” (sign-off) simulation library upon which the downstream IC design is based. A large percentage of the library development effort is invested in coding and verifying custom or special function cells that cannot be easily represented by traditional gates such as AND, OR, and are naturally encoded as look-up tables. These look-up tables are called table-based descriptions
14
and are stored in the implementation library
12
. The tables
14
are created in the target simulator's language; for example user-defined primitive (UDP) tables in Verilog or VITAL tables in VHDL as described in: IEEE Standards Department, “IEEE Standard VHDL Language Reference Manual,” IEEE-1076-1987, IEEE, NY, 1988; IEEE Standards Department, “Verilog Hardware Description Language,” IEEE-1364, 1994; and IEEE Standards Department, “Standard VITAL ASIC Modeling Specification,” IEEE P1076.4, July 1995.
As shown in
FIG. 1
, the first library
12
may be used for simulation
16
a
, emulation
16
b
and verification
16
c
. However, an equivalent structural “test” library
22
is needed for test generation
20
a
and formal verification
20
b
. The structural library
22
is needed because tools such as test generation
20
a
and formal verification
20
b
do not directly accept simulation-table models
14
. Therefore, the structural test library
22
is created to support test generation processes
20
a
and formal verification
20
b.
The most engineering-time consuming process of the IC design process
10
is manually translating (e.g., hand-coding) the table-based models
14
(akin to truth-tables) from the simulation library
12
into structural models
24
in the test library
22
. The manual translation is labor intensive and error prone and involves explicitly instantiating gates and manually connecting the gates into an equivalent structure. Moreover, once the manually generated structural models
24
are generated, they require verifying their logical equivalence
18
, which consumes additional design time. It would be advantageous to make the above IC design process
10
more efficient and cost effective.
Accordingly, what is needed is a system and method for reducing the complexity of an IC design process by eliminating and/or increasing the efficiency of one or more steps of the IC design process. What is also needed is a system and method for reducing the amount of hand-coded descriptions required in the IC design process. In view of the above needs, the present invention provides a system and method for increasing the efficiency of an IC design process to thereby provide a faster, more cost effective and more accurate IC design process. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
SUMMARY OF THE DISCLOSURE
A system and method are described for generating gate level descriptions from simulation tables for formal verification. Implementation libraries contain table-based descriptions of user defined primitives (UDPs), various-strength primitives, hierarchical structural cells and non-functional constructs, such as timing and simulation assertion checks. According to one embodiment, the present invention provides a library reader that is adapted for accessing an implementation library, including UDPs, and translating the implementation library into gate-level descriptions. The present invention also provides a model builder that optimizes and flattens the gate-level descriptions to create ATPG models that can be directly used by ATPG processes. The present invention also provides a translator that maps the primitives of the ATPG models into primitives of FV models that can be directly used by FV processes. Subsequently, the translated implementation library can be formally verified against a reference library. In addition, a gate level design that is based on the original implementation library can be formally verified against a reference design.
In accordance with the present invention, some UDPs can be directly translated into gate-level models that are usable by both ATPG and FV processes. However, for more complex UDPs, ATPG processes and FV processes may have different requirements. In order to create a single, common model that can be shared by both ATPG processes and FV processes, the library reader of the present invention eliminates non-functional circuitry, translates primitive strengths and extracts clock dominance from the UDPs. Further, the model builder propagates tied values and replaces equivalent latches and flip-flops while constructing the ATPG models. Consequently, the single, common model is augmented with a few bits of extra information, or, in some cases, changed in minor ways to accommodate different requirements of ATPG and FV.
For combinational table-based descriptions, the library reader of one embodiment of the present invention utilizes ordered ternary decision diagram (OTDD) graphs with input reordering to extract prime, non-redundant cube sets that can include high level functions (e.g., XOR, XNOR, MUX). For sequential table-based descriptions, a reduced or “clock” based OTDD graph is generated from which data and clock signals are identified and characterized. Input reordering is done and a complete sequential OTDD graph is generated, followed by port separation and characterization of the sequential element (e.g., latch, flip-flop, 2-latches). Clock and data functions are then con
Anastasakis Demosthenes
Wohl Peter
Smith Matthew
Synopsys Inc.
Thompson A. M.
Wagner , Murabito & Hao LLP
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