System and methods for pre-artwork signal-timing...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06954915

ABSTRACT:
Systems and methods for pre-artwork timing verification of an integrated circuit design are provided. A representative system includes a computer and a memory element associated with the computer, the memory element configured to store information related to a contemplated integrated circuit design and model functional blocks of the integrated circuit responsive to the expected signal timing behavior of signals that traverse a functional block of interest. A representative method includes the following steps: acquiring circuit information that represents a plurality of functional blocks and a plurality of conductors of a contemplated integrated circuit, where the functional blocks are modeled by a plurality of signal characteristics; receiving timing constraints used in designing each respective functional block; generating a representation of each functional block; and applying the representation in a static timing analyzer.

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patent: 2004/0015801 (2004-01-01), Mielke et al.

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