System and methods for performing cache latency diagnostics in s

Details System and methods for performing cache latency diagnostics in s System and methods for performing cache latency diagnostics in s

1998-08-07

2000-06-27

Thai, Tuan Vai

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711118, 711154, 711167, 710 18, G06F 1200, G06F 1300

Patent

active

060818689

ABSTRACT:
An integrated diagnostics system within a processing system for monitoring and identifying performance problems within the processing system. The processing system including at least one processor and at least one memory unit, wherein the processor is operable to read one or more addressable memory locations within the memory unit. The integrated diagnostics system including an integrated monitor for counting cache misses and idle time suffered by the processor waiting to read a first addressable memory location within the memory unit.

REFERENCES:
patent: 5845310 (1998-12-01), Brooks

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