Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2008-12-23
2009-11-03
Sorrell, Eron J (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S036000, C710S040000, C710S041000, C711S150000, C711S151000
Reexamination Certificate
active
07613850
ABSTRACT:
A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.
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Auernhammer Florian Alexander
Clauberg Rolf
Doering Andreas Christian
Dragone Silvio
Gabrani Maria
International Business Machines - Corporation
Sorrell Eron J
Thorne & Halajian, LLP
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