Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-08
2006-08-08
Sparks, Donald (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S054000, C711S122000, C711S145000, C712S225000
Reexamination Certificate
active
07089364
ABSTRACT:
A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.
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Pekkala et al., “Gathering Store Instructions In a Superscalar Processor”, Sep. 1996, IBM Technical Disclosure Bulletin, vol. 39, No. 09, pp. 103-106.
Arimilli Ravi Kumar
Cargnoni Robert Alan
Shen Hugh
Williams Derek Edward
Dillon & Yudell LLP
International Business Machines - Corporation
Salys Casimer K.
Savla Arpan
Sparks Donald
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