System and method to reduce jitter in digital delay-locked loops

Details System and method to reduce jitter in digital delay-locked loops System and method to reduce jitter in digital delay-locked loops

1996-02-29

1998-08-04

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327148, 327149, H03D 324

Patent

active

057906122

ABSTRACT:
The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.

REFERENCES:
patent: 4805195 (1989-02-01), Keegan
patent: 5297179 (1994-03-01), Tatsumi
patent: 5457718 (1995-10-01), Anderson et al.
patent: 5459766 (1995-10-01), Huizer et al.
patent: 5471502 (1995-11-01), Ishizeki
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5574756 (1996-11-01), Jeong

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