System and method to reduce cycle time by performing column...

Details System and method to reduce cycle time by performing column... System and method to reduce cycle time by performing column...

2000-02-22

2003-09-02

Gossage, Glenn (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C365S193000, C365S233100

Reexamination Certificate

active

06615331

ABSTRACT:

BACKGROUND
The invention relates to reducing cycle time in a memory device, such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM) device, for example.
A computer system typically includes semiconductor memory devices to store data structures and program code, and it is often desirable to improve the speed at which a central processing unit (CPU) of the system accesses these memory devices. Typically, the memory devices set the rate at which the CPU may communicate with the devices.
For example, in a synchronous dynamic random access memory (SDRAM), the signals that are depicted in
FIGS. 1
,
2
,
3
and
4
may occur in association with a write operation, and as described below, the SDRAM may introduce delays in the processing of the write operation. For example, in association with the write operation, the SDRAM receives signals (from a memory bus) that indicate a memory address. The SDRAM decodes these signals to produce column select signals (indicated by reference numeral
9
in
FIG. 2
) that indicate the columns of the targeted memory cells. When the address signals are decoded, circuitry of the SDRAM asserts an internal address valid strobe signal called INT_ADD_VALID (see FIG.
4
). As depicted in
FIG. 4
, the INT_ADD_VALID signal may be asserted near time T
0
to indicate the availability of the decoded address.
Before the internal write operation to the targeted memory cells begins, the SDRAM performs redundancy checks to determine if one or more redundant columns of memory cells should be used. The time to perform these redundancy checks typically introduces a latency to the write operation (as depicted by reference numeral
10
in FIG.
3
), a latency that delays the internal write operation from beginning on the positive edge of a CLK signal (see
FIG. 1
) at time T
0
to beginning after the positive edge at time T
1
. In this manner, at time T
1
, circuitry of the SDRAM may pulse high (as indicated by a pulse
8
in
FIG. 3
) a column address latch, or trap, signal (called CAT) to latch the column select signals to begin an internal write operation to store data in the memory cells.
Another type of memory device is a double data rate (DDR) SDRAM. Exemplary memory bus signals that typically are associated with writing data to the DDR SDRAM are depicted in
FIGS. 5
,
6
,
7
,
8
,
9
,
10
and
11
. More particularly, the DDR SDRAM captures data from the memory bus using the positive and negative edges of a data strobe signal (called DQS) that is furnished to the memory bus by a memory controller. In this manner, in association with a write operation, the memory controller furnishes data signals to the memory bus (to which the DDR SDRAM is coupled) and drives a DQS strobe line with the DQS signal to trigger the capture of data by the DDR SDRAM.
Because the data and data strobe signals propagate across the memory bus from the memory controller to the DDR SDRAM, the DDR SDRAM must be capable of accommodating a wide range of possible propagation delays for these signals. For example, the minimum time at which the DQS signal may arrive at the DDR SDRAM is depicted by the DQS
MIN
signal of FIG.
9
and is shown in relationship to its associated data signals (represented by DATA
MIN
in FIG.
8
). Likewise, the maximum time at which the DQS signal may arrive at the DDR SDRAM is depicted by the DQS
MAX
signal of
FIG. 11
, and the corresponding DATA
MAX
data signals are depicted in FIG.
10
. To accommodate the worst case scenario (i.e., the maximum delay time), the DDR SDRAM typically does not assume its captured data is valid until time T
4
. Thus, accommodating this worst case scenario may introduce a latency to the write operation. Furthermore, the performance of a column redundancy check by the DDR SDRAM may introduce an additional latency time into the processing of the write operation.
Thus, there is a continuing need for a memory device that addresses one or more of the problems stated above.
SUMMARY
In one embodiment of the invention, a method usable with a memory device includes receiving a data strobe signal from a memory bus and capturing data that is associated with a write command from the memory bus in synchronization with the data strobe signal. A column redundancy check is performed in response to an address that is associated with the write command, and the beginning of an internal write operation to a memory cell array of the memory device is synchronized to a clock signal.
Advantages and other features of the invention will become apparent from the following description, the drawing and from the claims.


REFERENCES:
patent: 6061292 (2000-05-01), Su et al.
patent: 6067260 (2000-05-01), Ooishi et al.
patent: 6188638 (2001-02-01), Kuhne
patent: 6205046 (2001-03-01), Maesako
patent: 6215710 (2001-04-01), Han et al.

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