Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-15
2001-08-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S599000, C438S587000, C438S637000
Reexamination Certificate
active
06281108
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to semiconductor chips. More particularly, it relates to the design of a semiconductor chip. Still more particularly, it relates to a system and method for providing power to the gates of a semiconductor chip.
2. Related Art
An essential part of any semiconductor chip is its internal power network. It is the internal power network that routes power and ground from the pins of the external packaging of the chip to the gates of the chip. In the past, engineers have built elaborated power networks to route power and ground from the top layer of a semiconductor chip down to the lowest layer of a semiconductor chip.
In a conventional system for providing power to the gates of a semiconductor chip, each layer of the chip comprises a series of long, parallel metal strips. The placement of the gates generally dictates the design of the lowest layer of the internal power network while Ohm's law dictates the design of the remaining layers of the internal power network. The gates of a typical chip are formed more or less uniformly across the entire base of a chip. This distribution of gates means that power and ground must be available everywhere at the lowest layer of the chip to power the gates. Conventionally, power and ground are made available at the lowest layer of a chip by depositing a series of long, parallel metal strips. The gates of the chip are formed between these long, parallel metal strips. This arrangement ensures that every gate has access to both power and ground. While any system or method that routes power from one layer of the chip to another layer of the chip, without excessive voltage drop, may be used to route power from the top of the chip down to the lowest layer of the chip, engineers have conventionally made every layer of the internal power network out of long, parallel metal strips. These long, parallel metal strips at each layer of the chip are electrically connected to one another using vias.
This conventional system and method of routing power from the top layer of the chip down to the lowest layer of the chip has many drawbacks, however. For example, the elaborate internal power networks built by engineers in the past occupy a significant portion of the total routing area of a semiconductor chip. Using known internal power networks therefore significantly reduces the total routing area of a chip available for routing gate signal, and it complicates the design of a semiconductor chip. Furthermore, using known internal power networks makes semiconductor chips larger than they otherwise need to be and thereby increases the overall cost of a chip. Using known internal power networks also limits gate density.
What is needed is a simpler system and method for providing power to the gates of a semiconductor chip. As will be described in detail below, the present invention overcomes the drawbacks of the conventional system and method for providing power to the gates of a chip.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method for routing power and ground in a semiconductor chip using stacked vias. The system and method avoids using long, parallel metal strips on each layer of a chip to route power and ground from one layer of the chip to another layer of the chip.
In one embodiment, power or ground is routed between a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via of this embodiment comprises, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip.
In another embodiment, a plurality of metal strips for routing power or ground are located at a first metal layer and a plurality of stacked vias are used to connect the plurality of metal strips located at the first metal layer to a metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer.
In still another embodiment, a plurality of metal strips for routing power or ground are located at a first metal layer and a plurality of stacked vias are used to connect the plurality of metal strips located at the first metal layer to a plurality of metal strips located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer.
Further features of the present invention are described in detail below with reference to the accompanying drawings.
REFERENCES:
patent: 5742099 (1998-04-01), Debnath et al.
Tom Burd,Low Power CMOS Library Design Methodology(A HyperText Book) (created Sep. 27, 1995; visited Oct. 14, 1999)<http://infopad.eecs.berkeley.edu/infopad-ftp/theses/low.power.CMOS.library.MS/>.
Shohji, R. et al., “High Reliability Tungsten-Stacked Via Process with Fully Converted TiAl3Formation Annealing,”IEEE Transactions on Semiconductor Manufacturing, vol. 12, No. 3, Aug. 1999, pp. 302-312.
Anya Igwe U.
Silicon Graphics Inc.
Smith Matthew
Sterne Kessler Goldstein & Fox PLLC
LandOfFree
System and method to provide power to a sea of gates... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method to provide power to a sea of gates..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method to provide power to a sea of gates... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2479928