Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-07-10
2000-03-28
Robertson, David L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, 711135, G06F 1300
Patent
active
060444401
ABSTRACT:
A system and method of transferring data in multi-cache systems. The method includes transmitting a first segment of a data stream from a first cache to a second cache. The method also includes retransmitting the first segment of the data stream from the second cache to a main memory. The method further includes generating a second segment of the data stream and completing a transfer of the second segment to the first cache before completing the retransmission of the first segment from the second cache to the main memory.
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Jouppi, N. P.; Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers; 17th Ann. Int. Symp. on Computer Architecture; May 1990; pp. 364-373.
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Smith, Alan Jay; Sequential Program Prefetching in Memory Hierarchies; Computer; Dec. 1978; pp. 7-21.
Intel Corporation
Robertson David L.
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