Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07877714
ABSTRACT:
A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
REFERENCES:
patent: 7475366 (2009-01-01), Kuemerle et al.
patent: 7627836 (2009-12-01), Culp et al.
patent: 2005/0107967 (2005-05-01), Patel et al.
Anemikos Theodoros E.
Chadwick Laura S.
Lichtensteiger Susan K.
Polson Anthony D.
Spence Bickford Jeanne P.
Chiang Jack
International Business Machines - Corporation
Kotulak Richard
Roberts Mlotkowski Safran & Cole P.C.
Tat Binh C
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