Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
2000-01-04
2004-11-09
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C703S013000, C709S223000
Reexamination Certificate
active
06816829
ABSTRACT:
TECHNICAL FIELD
On a computer network system, the present invention is involved in the area of independently verifying the Execution Rate of individual tasks by a device, through simulation.
BACKGROUND OF THE INVENTION
In recent years, “Simulation” has been used as a method for verification of logical correctness of complex electronic circuit designs. Simulation in broad terms can be considered as the creation of a model which, if subjected to arbitrary stimuli, responds in a similar way to the manufactured and tested design. More specifically, the term “simulation” is typically used when such a model is implemented as a computer program. Simulation saves a significant amount of time and financial resources because it enables designers to detect design errors before the very expensive manufacturing process is undertaken. Moreover, the design process itself can be viewed as a sequence of steps where the initial general concept of a new product is being turned into a detailed blueprint. Detecting errors at the early stages of this process also saves time and engineering resources.
Many computer systems have a main device through which data flows to and from several other secondary devices. The main device has to execute bus transfers with each of the other devices at a required rate. A common problem associated with this type of device is ensuring and verifying that the system can meet the execution rate requirement of the transmit and receive paths between the main device and each secondary device.
SUMMARY OF THE INVENTION
The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through “simulation”. The present invention further describes a scenario in which a system has a main device through which data flows “to and from” other devices; however, bus transfers must fall within required rates.
In the present invention, a simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. Many systems have a main device through which data flows to and from several other secondary devices. The problem is to ensure that the device under test (DUT), can provide adequate bandwidth to and from each of the devices in the system.
Therefore a major embodiment of the present invention solves this problem of ensuring adequate bandwidth, by surrounding the DUT with models capable of providing random bursts across each bus. Yet another embodiment is that the present invention performs measurements on each individual bus against a performance criteria during each of the bursts, even when the burst rate across a particular bus is changing from one burst to the next. Part of that measurement is predicting the latency of the DUT. That is, the ability of the DUT to respond to a burst request in a timely fashion.
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Technical Disclosure Bulletin 12-70, Determining Instruction Rates of Computer Processors, A. L. Anthony and H. K. Watson p. 2019-2021.
Technical Disclosure Bulletin 12-88, “Instruction Execution Rate Performance Measurements on a Pipelined Multi-Function Unit Processor”, J. R. Rodriguez. P. 378-385.
Clark Robert Franklin
Likovich, Jr. Robert Brian
Rumph Darryl Jonathan
Winemiller Chad Everett
Cockburn Joscelyn G.
Craig Dwin M.
International Business Machines - Corporation
Kraft Paul
Teska Kevin J.
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