System and method to establish an adjustable on-chip impedance

Details System and method to establish an adjustable on-chip impedance System and method to establish an adjustable on-chip impedance

2005-09-06

2005-09-06

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S034000

Reexamination Certificate

active

06940303

ABSTRACT:
A method to establish an adjustable on-chip impedance within a predetermined range that involves establishing a reference current for the adjustable on-chip impedance and applying this reference current to the adjustable on-chip impedance. A voltage produced by applying the reference current to the adjustable on-chip impedance is sensed and compared with the comparator or other similar processor to a reference voltage. This comparison allows the adjustable on-chip impedance to be tuned when the comparison of the sense voltage and the reference voltage is unfavorable. Tuning the impedance results in an impedance value within a predetermined range that accounts for variances of both the reference current and reference voltage.

REFERENCES:
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6603329 (2003-08-01), Wang et al.
patent: 6836144 (2004-12-01), Bui et al.

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