Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2002-06-05
2004-12-28
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S063000, C365S210130, C365S230060
Reexamination Certificate
active
06836427
ABSTRACT:
TECHNICAL FIELD
This invention relates to DRAM devices. More particularly, the present invention is directed to DRAM devices employing open digitline array architecture.
BACKGROUND OF THE INVENTION
As is well known in the art, because the charged stored in dynamic random access memory (“DRAM”) cells is highly transitory in nature, the contents of DRAM cells must be refreshed tens or hundreds of times per second. Sense amplifiers typically are used to refresh the contents of the DRAM cells. A sense amplifier compares voltages received on two digitlines, an active digitline and a reference digitline. The sense amplifier measures which of the two digitlines carries a higher voltage, and then drives the digitline carrying the higher voltage toward Vcc and the digitline carrying the lower voltage toward ground.
Prior to the refreshing of each DRAM cell, the active and reference digitlines are each equilibrated by isolating them from storage cells and precharging them to Vcc/2. To actually refresh the DRAM cell, the DRAM cell's access transistor is enabled to connect the DRAM cell's capacitor to the active digitline. Once the DRAM cell's access transistor is enabled, if the charge stored in the DRAM cell's capacitor is a high voltage charge, the voltage on the active digitline will increase to a level at least slightly higher than Vcc/2, while the voltage on the reference digitline remains at Vcc/2. The sense amplifier will then drive the active digitline toward Vcc and the reference digitline toward ground. Conversely, if the charge stored is a low voltage charge, the voltage on the active digitline will drop to a level at least slightly lower than Vcc/2 while the voltage on the reference digitline remains at Vcc/2. The sense amplifier will then drive the active digitline toward ground and the reference digitline toward Vcc. After the sense amplifier has driven the digitlines toward complementary voltages, the DRAM cell's access transistor could be disabled, storing the resulting high or low voltage charge in the DRAM cell's capacitor.
DRAM cells, as also is well known in the art, typically are refreshed a row at a time. The access transistor of each DRAM cell in each row is connected to a word line which enables the access transistor for every DRAM cell in that row. Generally, each column of DRAM cells is equipped with its own sense amplifier which is coupled to digitlines for each column, allowing for the entire row to be refreshed at one time. In refreshing a row of DRAM cells, current and voltage disturbances result across the array of DRAM cells and the array's cell plates as power consumed by the sense amplifiers increases to drive digitlines toward complementary voltages.
The active digitlines and reference digitlines may be connected to the same sub-array or different sub-arrays depending upon the array architecture of the device.
FIGS. 1 and 2
illustrate the two predominant array architectures.
FIG. 1
shows a folded digitline array architecture sub-array
100
. The folded digitline array architecture is so named because, in the physical manifestation of the devices, the digitlines
102
actually are folded around each other between each memory cell
104
. For visual simplicity,
FIG. 1A
does not show the actual folding of the digitlines
102
; instead, the memory cells
104
are each depicted with the same orientation connected to two complementary digitlines
102
. A sense amplifier
106
is coupled to digitlines
102
from each column
108
of memory cells
106
, with the digitlines
102
connected to alternate memory cells
104
in each column. It is significant that each of the digitlines
102
connected to each sense amplifier
106
are connected to memory cells
104
in the same sub-array
100
.
FIG. 2
shows a pair of open digitline architecture sub-arrays
200
and
202
. Unlike the digitlines
102
(
FIG. 1
) in the folded digitline array architecture sub-array
100
, the digitlines
204
(
FIG. 2
) connected to each of the sense amplifiers
206
in the open digitline array architecture sub-arrays
200
and
202
are not connected to memory cells
208
in the same sub-array. To the contrary, each sense amplifier
206
is connected to one digitline
204
in one sub-array
200
and one digitline
204
in a second sub-array
202
. As can be readily inferred, the architecture is so named because the digitlines at the end of each sub-array are open to be connected to additional sub-arrays.
Each architecture has relative advantages over the other. For example, open digitline array architecture allows more memory cells
208
(
FIG. 2
) to be created per unit area. Theoretically, open digitline array architecture memory cells
208
require only 4F
2
or 6F
2
in area, where F represents the feature size, whereas folded digitline array architecture memory cells
104
(
FIG. 1
) require 8F
2
in area.
On the other hand, folded digitline array architecture enjoys an advantage over open digitline array architecture in common mode rejection of voltage disturbances which occur when, for example, as rows of memory cells
104
(
FIG. 1
) are activated as memory cells are read or refreshed. Because the sense amplifiers
106
in a folded digitline array architecture sub-array
100
are coupled to adjacent digitlines
102
in the same sub-array
100
, any voltage disturbances affecting the sub-array
100
affects both of the digitlines
102
approximately equally. Thus, when the sense amplifier
106
compares the voltages on the digitlines
102
, any voltage disturbances affecting the digitlines
102
should cancel out one another.
By contrast, in open digitline array architecture sub-arrays
200
and
202
(FIG.
2
), each of the sense amplifiers
206
is connected through digitlines
204
to memory cells
208
in two different sub-arrays
200
and
202
. A voltage disturbance might occur in one sub-array connected to the sense amplifier
206
, such as when a row is fired in that sub-array, whereas no such disturbance or a disturbance of a lesser degree might occur in the complementary sub-array where no activity is taking place. Consequently, a voltage carried by one of the digitlines
204
connected to a sense amplifier
206
may be increased or decreased by a voltage disturbance, while the other digitline
204
is undisturbed and, thus, its voltage remains unchanged. If such a disturbance were to cause the voltage on the active digitline to be in excess of Vcc/2 when the DRAM cell connected to that digitline was at a low voltage, the voltage on the active digitline might be greater than the voltage on the reference digitline. This would cause the sense amplifier
206
to read the wrong value or to refresh the DRAM cell with the wrong voltage. Thus, as a result of the voltage disturbance, the data of that DRAM cell stored a digit would be corrupted. Similarly, if a disturbance in the active array were to cause the voltage on the active digitline to be less than Vcc/2 when the DRAM cell connected to the active digitline was at a high voltage, the voltage on the active digitline might be less than the voltage on the reference digitline. As a result, the sense amplifier
206
might again read the wrong value from the DRAM cell or refresh the DRAM cell with the wrong voltage.
What is needed is a way to reduce the effect of voltage disturbances in open digitline array architecture memory arrays to avoid possible read and refresh errors. It is to reducing or eliminating this problem in open digitline array architecture DRAM devices that the present invention is directed.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method for introducing voltage disturbances into a reference sub-array to offset voltage disturbances that may occur in an active sub-array. The voltage disturbances may be introduced by connecting extra or otherwise unused rows of memory cells to currently unused digitlines in the reference sub-array to create voltage disturbances like those occurring in the active sub-array as a consequence of rows of m
Ingalls Charles L.
Kirsch Howard C.
Vo Huy T.
Auduong Gene
Dorsey & Whitney LLP
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