Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-12-19
2006-12-19
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S820000, C714S710000, C365S201000
Reexamination Certificate
active
07152192
ABSTRACT:
A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit comparison in the corresponding data word comparator; and reading the column status bits of each on-chip data word comparator.
REFERENCES:
patent: 5075892 (1991-12-01), Choy
patent: 5305261 (1994-04-01), Furutani et al.
patent: 5351213 (1994-09-01), Nakashima
patent: 5428575 (1995-06-01), Fudeyasu
patent: 5539699 (1996-07-01), Sato et al.
patent: 5928373 (1999-07-01), Yoo
patent: 5961653 (1999-10-01), Kalter et al.
patent: 5974579 (1999-10-01), Lepejian et al.
patent: 6061813 (2000-05-01), Goishi
patent: 6088823 (2000-07-01), Ayres et al.
patent: 6259639 (2001-07-01), Hashizume
patent: 6263461 (2001-07-01), Ayres et al.
patent: 6694461 (2004-02-01), Treuer
patent: 6714466 (2004-03-01), Park et al.
patent: 6950334 (2005-09-01), Shimizu et al.
Brummel Karl P.
Hill J. Michael
Mellinger Todd
Hewlett--Packard Development Company, L.P.
Tu Christine T.
LandOfFree
System and method of testing a plurality of memory blocks of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method of testing a plurality of memory blocks of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method of testing a plurality of memory blocks of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3656654