System and method of retiring store data from a write buffer

Details System and method of retiring store data from a write buffer System and method of retiring store data from a write buffer

1996-07-31

1999-05-25

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711118, 711169, 395591, 395872, G06F 1208

Patent

active

059078600

ABSTRACT:
A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes). are also disclosed.

REFERENCES:
patent: 4760520 (1988-07-01), Shintanti et al.
patent: 5423048 (1995-06-01), Jager
patent: 5438670 (1995-08-01), Baror et al.

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